RAL model byte_en

UVM
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1

I see few prerequisites for using byte_en in RAL model

To write a register field individually,

the underlying bus must support byte enables, and
the field must be the sole occupant of the byte lane(s).
If both of them are true, then set

the supports_byte_enable property of the uvm_reg_adapter, and
the individually accessible argument of the configure function of the uvm_reg_field. [credits to cluelogic]

if I have register with four register fields each of width 1 byte , If I have to write into only 2 fields, should I have to use two write functions?
ral_model.reg_name.field1.write(status, 0x8) //byte_en is 0x1
ral_model.reg_name.field2.write(status, 0x8) //byte_en is 0x2

is it possible to do this in single write by setting byte_en=0x3?

2

In reply to KranthiDV:

byte_en is only used if the bus is smaller than the register width.
See the UVM Reference Manual
byte_en
uvm_reg_byte_en_t byte_en
Enables for the byte lanes on the bus. Meaningful only when the bus supports byte enables and the operation originates from a field write/read.

3

In reply to chr_sue:
byte_en is only used if the bus is smaller than the register width

Isn’t other way around?

I am using a APB interface of 32 bit PWDATA/PRDATA with 4 BIT PSTRB. And my register width is also 32 bit.
I am assuming I can map PSTRB to byte_en.

I am aware that I can do below .
ral_model.reg_name.field1.write(status, 0x8) //PSTRB is 4’b0001
ral_model.reg_name.field2.write(status, 0x8) //PSTRB is 4’b0010

I want to know if I can converge above two APB writes to one APB write with PSTRB=4’b0011.