I have a scenario where designer has updated the default value of uvm_reg_field ( field1 ) of a particular register .
[ Previously the default value of the register was 0 which has been now updated to 1 ]
So for now we pass a run-time switch to bypass this instead of generating new RAL files .
(1) For bit_bash_seq ::
Before I start the bit_bash_seq ( in main_phase ) I use "set_reset" method for the field ( in configure_phase )
// In configure_phase()
rm_h.REG_BLOCK.REG.field1.set_reset( 32'h1 ) ;
But when I start the bit_bash seq I get a mismatch error for the field1 since it still expects a default value of 0 .
( In function build() , where the configure method() is called for field1 the reset value was specified as 0 )
I expected the reset value be updated .
But I Observe mismatch from bit_bash_seq for field1
(2) For hw_rst_seq ::
Before I start the hw_rst_seq ( in main_phase ) I use "predict" N "read" methods for field1 .
// In main_phase()
rm_h.REG_BLOCK.REG.field1.predict( 32'h1 ) ;
rm_h.REG_BLOCK.REG.field1.read( status , read_data ) ; // Actual RTL register field1 gives value 1 , so no mismatch error !!
Even though the configure arg. is 0 the predict updates the mirrored value so I don't see any mismatch error on read .
However when I start hw_rst_seq after ( predict N read ) I get a mismatch error where it expects a value to be read back as 0
( Same as arg. to field1 configure method ) .
Since I do predict() N read() before I start hw_rst_seq , why is that I still see a mismatch error ?