RAL Complex address mapping using add_submap

Dear Verification Academy Team,

I m trying to setup complex address mapping in the RAL model. I want to connect same register model to the individual AXI write and
AXI read sequencer. I have created 2 address maps and used add_submap to add register block to the 2 address maps. Somehow it is
not working. For your better understanding i have added snippet code for you.

//************** Code in the regmodel****************** 
rand ral_block_mss_regs mss_regs; 

// Register maps for write and read 
uvm_reg_map axi_wr_map; 
uvm_reg_map axi_rd_map; 

// Creating write address map 
this.axi_wr_map = create_map("axi_wr_map", 0, 4, UVM_LITTLE_ENDIAN, 0); 
this.mss_regs = ral_block_mss_regs::type_id::create("mss_regs",,get_full_name()); 
this.mss_regs.configure(this, ""); 
this.mss_regs.build(); 
this.axi_wr_map.add_submap(this.mss_regs.default_map, `UVM_REG_ADDR_WIDTH'h2000000); 

// Creating read address map 
this.axi_rd_map = create_map("axi_rd_map", 0, 4, UVM_LITTLE_ENDIAN, 0); 
this.axi_rd_map.add_submap(this.mss_regs.default_map, `UVM_REG_ADDR_WIDTH'h2000000); 

//***************** Code in the environment top**************** 

// Setting AXI write sequencer to the register map 
regmodel.axi_wr_map.set_sequencer( .sequencer(m_axi_env.q_master_agent[15].m_write_sequencer), .adapter(reg_adapter_h) ); 
// Setting AXI read sequencer to the register map 
regmodel.axi_rd_map.set_sequencer( .sequencer(m_axi_env.q_master_agent[15].m_read_sequencer), .adapter(reg_adapter_h) ); 

// Setting auto predictor 
regmodel.axi_wr_map.set_auto_predict(1); 
regmodel.axi_rd_map.set_auto_predict(1); 

//***************** Test case******************** 

e.regmodel.mss_regs.cfg_tgen_cfg14.write(reg_status, 'h5a5b5c5d, .map(axi_wr_map)); 
e.regmodel.mss_regs.cfg_tgen_cfg14.read(reg_status, reg_data, .map(axi_rd_map));

Error reported:
reporter [RegModel] Map ‘regmodel.mss_regs.uvm_reg_map’ is already a child of map ‘regmodel.axi_wr_map’. Cannot also be a child
of map ‘regmodel.axi_rd_map’

Thanks,
Madhu

In reply to chmeher:

The problem that you are facing is related to
https://verificationacademy.com/forums/uvm/how-support-multiple-register-maps-soc-system-block-only-one-register-map