RAL Backdoor access

UVM
1

I was trying to wwrite through backdoor access in my RAL model and I have given write access in configuration of reg_field and in reg_map, and the hdl path is also correct. even though it is showing error “attempting to write in top.DUT.RCNTRL (tb_top.dut_instance.reg_name) which does not have write access.” error is showing in RTL design, but ral model register has been updated.

2

In reply to shreebamnikar:

Could you please elaborate some more details, please. How do you write through backdoor?

3

In reply to chr_sue:

in register sequence class, in body task I am writing as follows:
reg_model.reg_name(status,value,UVM_BACKDOOR);

4

In reply to shreebamnikar:

peek and poke are dedicated for backdoor access. Would you please try this.

5

In reply to chr_sue:

same error I am getting does not have write access.

6

In reply to shreebamnikar:

Could you please provide some more details about your register model (choose 1 register description which is RO).

7

In reply to shreebamnikar:

Can you show exact error from tool? Some simulators restrict accesses to internal registers to optimize for speed. There are flags to turn that off.

Srini
www.go2uvm.org

8

In reply to Srini @ CVCblr.com:
following is the error:

Starting RAL read write BACKDOOR sequence
ERROR: VPI VISNOW
Attempting to place a value into top.RTC.RTCMR which does not have write access.
…/rtl/RTL_RTC/Rtc.v, 117:
UVM_INFO @ 0: reporter [RegModel] Wrote register via DPI backdoor: rtc_rm.rtcmr=0xaaaaaaaa
UVM_INFO @ 0: reporter [RegModel] Read register via DPI backdoor: rtc_rm.rtcmr=0

9

In reply to chr_sue:
this is my reg model:

class rtc_reg_block extends uvm_reg_block;
`uvm_object_utils(rtc_reg_block)

RTCMR_REG rtcmr;

RTCDR rtcdr;

uvm_reg_map rtc_map;

function new( string name=“rtc_reg_block”);
super.new(name,UVM_NO_COVERAGE);
endfunction

virtual function void build();
rtcmr=RTCMR_REG::type_id::create(“rtcmr”);
rtcmr.configure(this,null,“”);
rtcmr.build();
rtcmr.add_hdl_path_slice(“RTCMR”,'h 0,32); //[31:0]RTCMR in DUT read write reg

rtcdr=RTCDR::type_id::create(“rtcdr”);
rtcdr.configure(this,null,“”);
rtcdr.build();
rtcdr.add_hdl_path_slice(“RtcValue”,'h0,32); //[31:0]RtcValue in DUT read only reg

rtc_map=create_map(“rtc_map”,'h 00,4,UVM_LITTLE_ENDIAN);

rtc_map.add_reg(rtcmr,'h 1,“RW”);
rtc_map.add_reg(rtcdr,'h0,“RO”);
lock_model();
endfunction
endclass

10

In reply to shreebamnikar:

In reply to chr_sue:
this is my modified reg model added HDL path: please refer this
class rtc_reg_block extends uvm_reg_block;
`uvm_object_utils(rtc_reg_block)
RTCMR_REG rtcmr;
RTCDR rtcdr;
uvm_reg_map rtc_map;
function new( string name=“rtc_reg_block”);
super.new(name,UVM_NO_COVERAGE);
endfunction
virtual function void build();
rtcmr=RTCMR_REG::type_id::create(“rtcmr”);
rtcmr.configure(this,null,“”);
rtcmr.build();
rtcmr.add_hdl_path_slice(“RTCMR”,'h 0,32); //[31:0]RTCMR in DUT read write reg
rtcdr=RTCDR::type_id::create(“rtcdr”);
rtcdr.configure(this,null,“”);
rtcdr.build();
rtcdr.add_hdl_path_slice(“RtcValue”,'h0,32); //[31:0]RtcValue in DUT read only reg
rtc_map=create_map(“rtc_map”,'h 00,4,UVM_LITTLE_ENDIAN);
rtc_map.add_reg(rtcmr,'h 1,“RW”);
rtc_map.add_reg(rtcdr,'h0,“RO”);
add_hdl_path(“top.RTC”,“RTL”);
lock_model();
endfunction
endclass

11

In reply to shreebamnikar:

I believe your problem is in your register model. Unfortunately I do not see the definitions for the regs. I am recommending you should follow the register example from the Verification Academy.
The model hierarchy is:
reg_field
reg
block
map.

12

In reply to shreebamnikar:

I guess you use NC, you need to enable access capability- see your manual and this link http://www.lirmm.fr/~bosio/tmax_olh/Content/tpv_ug/4.troubleshoot_verilog_dpv/troubleshooting_verilogdpv_ncverilog.htm

Good luck
Srini
www.go2uvm.org

13

In reply to chr_sue:

I have defined in another file that i have forgot to mention in above post , my register model is perfect because I did frontdoor operation successfully.

14

In reply to shreebamnikar:
OK, if you believe your model is correct then it might be a tool issue.
But I’m not sure if your model is really correct. Because the frontdoor access does not breack the access rights as you can do with the backdoor access.

15

In reply to chr_sue:
problem has been resolved, this was simulator tool problem “-access rw” should be included in makefile.