A race condition between threads concurrently accessing the register model

UVM
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1

Hi All,

I am facing the below warning.

W:: UVM/FLD/SET/BSY: Setting the value of field “XXX” while containing register “YYY” is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

I have instantiated register model twice because I have replicated module in RTL and differentiated both module by base_address. When I am disabling the one module, read/write is working fine on another module and vice-versa. This issue is occurring only while trying to access both modules simultaneously. RAL instance are different, base address are different than don’t know how this warring is shouting.

Can someone please guide me if I am missing something to differentiate both module?

Thanks,
Devang

2

In reply to devangpatil:

Are you saying you were getting this error message regardless of which registers you are accessing in both models? This is going to be very hard to debug without seeing code, and probably too much code to post on a forum. You might have to reproduce the issue by creating a small test case containing a register model that you instantiate twice.