Questions to exercise my SystemVerilog, Assertions and UVM skills

Hey,
I’m looking for few sources where i can exercise my UVM, SystemVerilog and Assertions skills by answering few of the programming questions which can be completed within an hour.
Could you please suggest few links/materials/sources (preferably with solution but even otherwise its Okay )??
Cheers!!

In reply to vvv:

A commercial option with analysis is available at: http://www.verifjobs.com/tech-quiz/
There is also free version of these Quizzes on case to case basis. Contact via that link to learn more.

Regards
Srini

In reply to Srini @ CVCblr.com:

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