Question on uvm_port_base#(IF)

UVM
1

Hi,
I have a question on uvm_port_base class as follows :

  1. the uvm_port_base#(IF) parametrized class extends from IF and IF is also used as parameter with default value of uvm_void. UVM reference states that for TLM interfaces, IF parameter is always uvm_tlm_if_base#(T1, T2). Also uvm_tlm_if_base is a virtual class which declares all methods of TLM API. So all the classes like uvm_port, uvmexport, uvm*_imp would inherit the API methods from uvm_tlm_if_base. So while defining uvm_port_base#(IF), what is the necessity of defining IF as parameter. Does uvm_port_base declare member of the uvm_tlm_if_base type? Can someone explain please.

2.Also I came across a post on Internet saying that uvm_port_base#(IF) extends from IF and IF is also a parameter. This is done as a workaround for multiple interitance feature which System verilog does not support at present. (pls refer the link : uvm - uvm_port_base class derivation correct hierarchy - Stack Overflow)
In any case, even with this definition how is the multiple inheritance supported?

thanks,
-sunil

2

In reply to puranik.sunil@tcs.com:

This code (which came from the AVM) was written by the same person who wrote SystemC’s TLM API and followed the same pattern had SystemVerilog supported Multiple inheritance at the time. Someone just posted a “simplified” version of this TLM interface here. Even simplified it is still hard to follow.

Right now, uvm_tlm_if_base has combined all the TLM methods into a single class. Classes like uvm_put_port will override the put() and try_put() methods. If you attempt to call my_put_port.peek(), you get a run-time error message because all the methods in the uvm_tlm_if_base. With SystemVerilog’s interface class feature, you could inherit just method prototypes needed, and you would get an early compiler error if you tried to call a method that was not part of your uvm_*_port.