Question related to implementation of test bench architecture based on back pressure traffic

UVM
1

Hi,

We have this requirement.

  1. If packets are sent to same port then back pressure is generated. This causes RTL to create pause frame. Upon receiving this frame TB should stop sending anymore packets until the specified timer stops.
    This is what I am planning to do :
  • the scoreboard will detect the pause frame , put it in queue.
  • The reception on this frame will set a flag “stop_transmission” in “config file” (Q : is config file right place to set the flag ?)

Q: Now, I am kind of debating if driver or sequence should look at this flag. (I am leaning towards sequence to look at the flag), if sequence see the flag it should stop sending traffic till the counter is over.

So 2 questions :

  1. Is config file the right place to set/observe flags from driver/sequence/monitor ?
  2. Should I implement the traffic control mechanism (based on the flag) in driver or sequence ?

Thanks a bunch in advance !

2

Have you considered using assertions in the SV interface to create this flag? The driver can then make use of this flag. In my paper at http://systemverilog.us/papers/sva4scoreboarding.pdf
I show how assertions can make use of user-defined function call from sequence match items after the assertion reaches desired points. This may facilitate the detection of critical features (e.g., packets sent to same port) and the creation of flags to be used by the drivers or verification units.

3

In order to achieve a “separation of concerns”, the back-pressure condition should be detected in the driver, and it is the driver that should hold off sending more packets until the DUT is ready to receive more. The sequence shouldn’t need to know anything about the back-pressure.

In your agent, the monitor should detect the back-pressure condition and emit a transaction to analysis components such as scoreboards and functional coverage monitors to let them know that it has occurred.

If you take this approach, then your implementation will be modular and easier to use.

4

In reply to ben@SystemVerilog.us:

Thanks Ben ! It is very useful hint. I actually have frames coming in and it is decoded by monitor. I am using the forever loop to detect the frame and setting the flag in my monitor.
Assertion would be easier in the case where I had direct signal coming in.

5

In reply to mperyer:

Thanks ! I will put it in driver and also set a switch which allows driver to send incase you want to create error conditions etc. Also, I don’t have to modify all sequences.