Question about clock generation in test bench

UVM
1

Hi, all

I have to use multiple clocks in my simulation, for example clk_1Mhz, clk_2Mhz. how should I generate these three clock in top module?


initial begin
  clk_2Mhz = 1'b0;
  forever begin
    #0.5us clk_2Mhz = ~clk_2Mhz;
    // or use this: #0.5us clk_2Mhz <= ~clk_2Mhz;
  end  // forever
end // initial

and for the other one, which puzzled me a lot, seems caused cdc problem


initial begin
  clk_1Mhz = 1'b0;
  forever begin
    #1us clk_1Mhz = ~clk_1Mhz;
    // or use this: #1us clk_1Mhz <= ~clk_1Mhz;
    // or use this: @(posedge clk_2Mhz) clk_1Mhz <= ~clk_1Mhz;
  end  // forever
end // initial
2

In reply to EnRoute_zt:

What are the errors that you see? I would expect this to work -

initial begin
clk_2Mhz = 1’b0;
forever begin
#0.5us clk_2Mhz = ~clk_2Mhz;
end
end

initial begin
clk_1Mhz = 1’b0;
forever begin
#1us clk_1Mhz = ~clk_1Mhz;
end
end

3

In reply to tejapan:

Your code is definitely working. Maybe there is a problem with the timing setup, with respect to time unit and time resolution.