- Error: C:/questasim64_10.2c/uvm-1.1d/…/verilog_src/uvm-1.1d/src/macros/uvm_message_defines.svh(24): (vlog-2894) Class ‘fcs_host_sequence_c’ is parameterized. Parameterized nested classes currently not supported.
Like this above i got error in questsim can any one help to solve this one?
`ifndef FCS_HOST_DRIVER_C__SV
`define FCS_HOST_DRIVER_C__SV
class fcs_host_driver_c extends uvm_driver#(fcs_host_seq_item_c);
`uvm_component_utils(fcs_host_driver_c)
function new(string name="fcs_host_driver_c",uvm_component parent=null);
super.new(name,parent);
`uvm_info(get_type_name(),"new constructor called inside of the host sequencer",UVM_DEBUG)
endfunction:new
task run_phase(uvm_phase phase);
`uvm_info(get_type_name(),"starting of the host run phase",UVM_DEBUG)
forever begin
seq_item_port.get_next_item(req);
req.print();
seq_item_port.item_done;
#100;
end
`uvm_info(get_type_name(),"ending of the host run phase",UVM_DEBUG)
endtask:run_phase
endclass:fcs_host_driver_c
`endif