Query Related TLM port

Hi All,

I am facing a strange error when using TLM fifo,put and get port. I am not able to get the item through get port which was put to put port.
Code is similar like code below.


class one;
uvm_put_port #(item1)  put_port;
uvm_tlm_fifo #(item1)   fifo_h;

function build_phase();
put_port =new("put_port",this);
fifo_h =   new("fifo_port",this);
endfunction

function connect_phase();
	put_port.connect(fifo_h.put_export);
endfunction
endclass

class two;
uvm_get_port #(item1)   get_port;
function build_phase();
    get_port = new("get_port",this);
endfunction
endclass

class env;
one o1;
two t2;
function connnect_phase();
	t2.get_port.connect(o1.fifo_h.get_peek_export);
endfunction
endclass

Class seq;
item i1;
task send item();
	p_sequencer.o1.put_port(i1);
endtask

class seq2;

task collect_item;
// DISPLAY STATEMENTS ARE PRINTED HERE

p_sequencer.t2.get_port(i1); // NOT ABLE TO GET THE ITEM.
endtask
endclass



Now I have used few debugs. Like i tried to monitor both fifo and get port using print statements in env class.
Like when i used following function to monitor

`uvm_info (“DEBUG”, " Fifo port size:%d", Try_get:%d", o1.fifo_h.used, t2.try_get(item1)),UVM_LOW)

I got following prints in below fashion
1st print Fifo_port size: 1, Try_get : 1
2nd print Fifo_port size: 0, Try get : 0
3rd print Fifo_port size: 0, Try get : 0

Now if i use following function to monitor.
`uvm_info (“DEBUG”, " Fifo port size:%d", Can_get:%d", o1.fifo_h.used, t2.can_get()),UVM_LOW)

I get print in following manner.
1st print Fifo_port size: 1, Can_get : 0
2nd print Fifo_port size: 1, Cry get : 0
3rd print Fifo_port size: 1, Cry get : 0

**
Please let me know why “try_get” can access the get port and get the item.
Why “can_get” and “get” cannot access or get the item.
Please help me in solving this issue.
**

Thanks

In reply to raku:

I do not understand why you do not use the uvm_sequencer and the tlm_fifo. The sequencer has the corresponding port and the tlm_fifo an export. There is no need to implement any uvm_put_port.