Hi ,
One of my interviewer is asking me.
Why we see si bugs ? As we did functional verification with fun & assert coverage: 100%, Code coverage is 100%, GLS reg is 100 % pass rate.
What are Testbench limitation making us not predict the si bugs in RTL verification ?
How to develop those skills/thinking as functional verification engineer ?
Thanks,
Karthik
In reply to karthik6037:
Code coverage can only tell you what logic has not been verified, or is unnecessary; it cannot tell what has been verified. It is completely disconnected from requirements.
Functional coverage and assertions can tell you which requirements have been verified. You need to track coverage to specific requirements to know when 100% of the requirements have been verified.
Of course there can always be bugs in the verification process that give you false positives.