// LOWER SEQUENCE
`include "lower_item.sv"
`include "upper_item.sv"
class lower_seq extends uvm_sequence #(lower_item);
`uvm_object_utils(lower_seq)
`uvm_declare_p_sequencer(lower_sequencer)
function new(string name = "lower_seq");
super.new(name);
`uvm_update_sequence_lib
`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
endfunction
upper_item u_item;
lower_item l_item;// req also same as l_item
virtual task pre_do (bit is_item);
if(is_item)
p_sequencer.upper_seq_item_port.get_next_time(u_item);
endtask
virtual task body();
`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
if (starting_phase != null)
starting_phase.raise_objection(this);
repeat(10) begin
`uvm_do(l_item);
end
if (starting_phase != null)
starting_phase.drop_objection(this);
endtask
virtual function void post_do(uvm_sequence_item this_item);
p_sequencer.upper_seq_item_port.item_done(this_item);
endfunction
endclass
//LOWER SEQUENCER
`include "lower_seq.sv"
class lower_sequencer extends uvm_sequencer #(lower_item);
`uvm_component_utils(lower_sequencer)
uvm_seq_item_pull_port #(upper_item) upper_seq_item_port;
function new(string name, uvm_component parent);
super.new(name,parent);
upper_seq_item_port = new ("upper_seq_item_port", this);
`uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
endfunction
endclass
I am getting following error…
`uvm_declare_p_sequencer(lower_sequencer)
|
ncvlog: *E,NOIPRT (lower_seq.sv,6|40): Unrecognized declaration ‘lower_sequencer’ could be an unsupported keyword, a spelling mistake or missing instance port list ‘()’ [SystemVerilog].
Please help me in this regard…
Thanks
Naveen