Problem while adding memory in ral model

UVM
,
1 
I got a problem while adding memory in RAL.
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     bit [7:0] mem0[256];                  //These are the memory blocks in DUT.They altogether work as a single memory i.e, [31:0]mem[256]
     bit [7:0] mem1[256];                  //i.e, mem[0] = { mem0[0] , mem1[0] , mem2[0] , mem3[0] }
     bit [7:0] mem2[256];                  //and the base address for mem[0] is 'h400
     bit [7:0] mem3[256];

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I took four memory blocks in my reg_blocks similar to DUT,but when I'm adding it to reg_map ,

      reg_map.add_mem(.mem(mem0),.kind("MEM"),.offset('h400)); //Here every mem offset value is same because 
      reg_map.add_mem(.mem(mem1),.kind("MEM"),.offset('h400)); //mem[0][31:0] = {mem0[0][7:0] , mem1[0][7:0] , mem2[0][7:0] , mem3[0][7:0]}
      reg_map.add_mem(.mem(mem2),.kind("MEM"),.offset('h400));
      reg_map.add_mem(.mem(mem3),.kind("MEM"),.offset('h400));

   I did like this but I think it don't work as expected.Can you please suggest me how to achieve this?