In reply to dave_59:
hey thanks for your response but 2 error are also coming, i have given sequence, virtual sequnce , tests, driver code …please check it. i am new to UVM , m not getting ACTUAL problem
//errors------------------------------------
UVM_ERROR @ 385: uvm_test_top.env_inst.agent_inst.seqr@@seq_inst [uvm_test_top.env_inst.agent_inst.seqr.seq_inst] Response queue overflow, response was dropped
385ns : Driver Send Transaction Request to Sequencer…
//warning---------------------------------
UVM_WARNING @ 0: uvm_test_top.env_inst.agent_inst.seqr@@seq_inst [uvm_sequence_base] Body definition undefined
//sequence class-----------------------------------------
//-------class sequence------------------------------
class and_sequence extends uvm_sequence #(and_transaction);//parameterized with the type of the transaction
`uvm_object_utils(and_sequence) //uvm factory....registration
and_transaction tx; //sequence item
function new(string name =" "); //constructor
super.new(name);
endfunction :new
task body();
endtask:body
endclass :and_sequence
class and_write_seq extends and_sequence;
`uvm_object_utils(and_write_seq)
// data members
and_transaction write_tx;
// constructor
function new (string name="");
super.new(name);
endfunction : new
// body
task body();
super.body();
`uvm_info("seq_body",$sformatf(" starting and_write_seq "),UVM_LOW)
write_tx = and_transaction::type_id::create("write_tx");
start_item(write_tx);
if(!write_tx.randomize() with {is_data==1; reset==0;})
`uvm_error("seq_body"," write_tx randomization failed")
finish_item(write_tx);
//wait for completion of burst
get_response(write_tx);
`uvm_info("seq_body",$sformatf(" and_write_seq ends "),UVM_LOW)
endtask : body
endclass : and_write_seq
class and_reset_seq extends and_sequence;
`uvm_object_utils(and_reset_seq)
// data members
and_transaction reset_tx;
// constructor
function new (string name="");
super.new(name);
endfunction : new
// body
task body();
super.body();
`uvm_info("seq_body",$sformatf(" starting and_reset_seq "),UVM_LOW)
reset_tx = and_transaction::type_id::create("reset_tx");
start_item(reset_tx);
if(!reset_tx.randomize() with {reset==1; is_data==0;})
`uvm_error("seq_body"," reset_tx_req randomization failed")
finish_item(reset_tx);
//wait for completion of burst
get_response(reset_tx);
`uvm_info("seq_body",$sformatf(" and_reset_seq ends "),UVM_LOW)
endtask : body
endclass : and_reset_seq
//-----------------virtual sequence-------------------------------------
//Virtual sequences
class and_vseq_base extends uvm_sequence #(uvm_sequence_item);
`uvm_object_utils(and_vseq_base)
function new(string name = “and_vseq_base”);
super.new(name);
endfunction
// Virtual sequencer handles
my_seqr my_seqr_inst;
// Handle for env config to get to interrupt line
//and_env_config m_cfg;
// This set up is required for child sequences to run
task body;
if(!uvm_config_db #(my_seqr)::get(null, get_full_name(), “my_seqr”, my_seqr_inst)) begin
`uvm_error(“CONFIG_DB_ERROR”, “and sequencer not found”)
end
/* if(!uvm_config_db #(and_env_config)::get(null, {“uvm_test_top.”, get_full_name()}, “and_env_config”, m_cfg)) begin
`uvm_error(“body”, “Cannot find and_env_config”)
end*/
endtask: body
endclass: and_vseq_base
// single and reset seq with random data
class and_reset extends and_vseq_base;
`uvm_object_utils(and_reset)
function new(string name = “and_reset”);
super.new(name);
endfunction
task body;
// issue reset seq
and_reset_seq reset_seq = and_reset_seq::type_id::create("reset_seq");
//call base virtual seq for sequencer's handle and cfg onject
super.body;
//start tx and rx sequences
fork
//at and_agent
reset_seq.start(and_seqr_inst);
join
endtask: body
endclass: and_reset
// single and reset seq with random data
class and_write extends and_vseq_base;
`uvm_object_utils(and_write)
function new(string name = “and_reset”);
super.new(name);
endfunction
task body;
// issue reset seq
and_write_seq write_seq = and_write_seq::type_id::create("write_seq");
//call base virtual seq for sequencer's handle and cfg onject
super.body;
//start and_write sequences
fork
//at and_agent
write_seq.start(and_seqr_inst);
join
endtask: body
endclass: and_write
//-------------driver-------------------------------------
/import uvm_pkg::;
`include “uvm_macros.svh”
*/
//------------------Driver----------------------------
class my_driver extends uvm_driver#(and_transaction);
`uvm_component_utils(my_driver) //uvm factory…registration
function new(string name, uvm_component parent); //constructor
super.new(name,parent);
endfunction
and_transaction req;
virtual dut_if vif;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// Get interface reference from config database
begin
if(!uvm_config_db#(virtual dut_if)::get(this, "", "dut_vif", vif))
`uvm_error("", "uvm_config_db::get failed")
end
endfunction
task run_phase(uvm_phase phase);
// First toggle reset
@vif.data_cb;
vif.reset=1;
#1;
vif.reset=0;
// Now drive normal traffic
forever
begin
$display("%tns : Driver Send Transaction Request to Sequencer...",$time);
seq_item_port.get_next_item(req);
//*********************************************************
// receive transaction from sequencer and
// convert to signal levels(drive to dut)
//*********************************************************
drive (req);
end
endtask
task drive(and_transaction req);
if(req.is_data==1) begin
run_data(req);
end
else begin
run_reset(req);
end
seq_item_port.item_done();
endtask : drive
// data drivers
task run_data(and_transaction req);
begin
$display("%tns : Driver Received Transaction from Sequencer...",$time);
@vif.data_cb;
vif.reset<=0;
vif.a<= req.a;
vif.b<= req.b;
end
endtask :run_data
//drive Reset Condition
task run_reset(and_transaction req);
if(req.reset==1)
begin
$display("%tns : Driver accompalish reset operation...",$time);
@vif.data_cb;
vif.reset <=1;
vif.a <= 0;
vif.b <= 0;
@vif.data_cb;
#100ns;
//wait for 100ns;
vif.reset <= 1'b0;//put inside cb
end
endtask :run_reset
endclass: my_driver
//---------------------test base class---------------------
//*********************************************************
// Include Environment Component
//*********************************************************
// include "env.sv" // include “sequence.sv”
//------------test-------------------------------------------
class my_base_test extends uvm_test;
`uvm_component_utils(my_base_test) //uvm factory…registration
my_env env_inst;
//and_sequence tx_seq;
//and_sequence seq_inst;
// Configuration objects
env_config env_config_inst;
function new(string name=“my_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
// env configuration
env_config_inst = env_config::type_id::create(“env_config”);
// Create the sequence
// seq_inst= and_sequence::type_id::create(“seq_inst”,this);
// Set the spi env config object
uvm_config_db #(env_config)::set(this, “*”, “env_config_inst”, env_config_inst);
// Create the enviornment
env_inst = my_env::type_id::create(“env_inst”, this);
endfunction:build_phase
endclass :my_base_test
//----------------------extends of test base class
class my_write_test extends my_base_test;
`uvm_component_utils(my_write_test) //uvm factory…registration
//------------------------------------------
// Methods
//------------------------------------------
// Standard UVM Methods:
extern function new(string name = “my_write_test”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
function void end_of_elaboration();
print();
endfunction : end_of_elaboration
endclass :my_write_test
function my_write_test::new(string name=“my_write_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction :new
function void my_write_test::build_phase(uvm_phase phase);
super.build(phase);
endfunction:build_phase
task my_write_test::run_phase(uvm_phase phase);
`uvm_info(“test”,$sformatf(" enter inside run_phase of my_write_test "),UVM_NONE);
and_write and_write_inst = and_write::type_id::create(“and_write_inst”);
// We raise objection to keep the test from completing
phase.raise_objection(this, “Test Started”);
// start sequence put on the sequencer
and_write_inst.start(env_inst.agent_inst.seqr);
`uvm_info(“test”,$sformatf("and_write seq starting "),UVM_NONE);
// #1000ns;
// uvm_report_info(“”,“Global Request”, UVM_LOW);
// global_stop_request();
// We drop objection to allow the test to complete
phase.drop_objection(this, “Test Finished”);
`uvm_info(“test”,$sformatf("and_write seq ending "),UVM_NONE)
endtask :run_phase
//------------extends of base test class-------------------------------------------
class my_reset_test extends my_base_test;
`uvm_component_utils(my_reset_test) //uvm factory…registration
//------------------------------------------
// Methods
//------------------------------------------
// Standard UVM Methods:
extern function new(string name = “my_reset_test”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
function void end_of_elaboration();
print();
endfunction : end_of_elaboration
endclass :my_reset_test
function my_reset_test::new(string name=“my_reset_test”, uvm_component parent=null); //constructor
super.new(name,parent);
endfunction
function void my_write_test::build_phase(uvm_phase phase);
super.build(phase);
endfunction:build_phase
task my_reset_test::run_phase(uvm_phase phase);
// uvm_info("test",$sformatf(" enter inside run_phase of PUT SEQUENCES ON SEQUENCER "),UVM_NONE); uvm_info(“test”,$sformatf(" enter inside run_phase of my_reset_test "),UVM_NONE);
and_reset and_reset_inst = and_reset::type_id::create(“and_reset_inst”);
// We raise objection to keep the test from completing
phase.raise_objection(this, “Test Started”);
// start sequence put on the sequencer
and_reset_inst.start(env_inst.agent_inst.seqr);
`uvm_info(“test”,$sformatf("and_reset seq starting "),UVM_NONE);
// #1000ns;
// uvm_report_info(“”,“Global Request”, UVM_LOW);
// global_stop_request();
// We drop objection to allow the test to complete
phase.drop_objection(this, “Test Finished”);
`uvm_info(“test”,$sformatf("and_reset seq ending "),UVM_NONE)
endtask :run_phase