Hi,
I am facing an issue with RAL when I do read/predict-mirror method.
my predict logic(bus2reg function) runs much before my monitor sees the valid transaction on bus,resulting in wrong data capture and causes data mismatch UVM_ERROR error.
- In adapter class, provides_responses is set to 0.(tried with 1 as well, but doesn’t seem to work)
- Auto predict mode is off.
----------------[ env ]-------------------
class my_env extends uvm_env;
`uvm_component_utils(my_env)
env_config h_env_cnfg;
agent h_agt;
reg_predictor h_predictor;
//NEW
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction : new
//BUILD
function void build_phase(uvm_phase phase);
super.build_phase(phase);
//GET THE ENV-CONFIGURATION HANDLE FOR CONFIG_DB
if(!uvm_config_db#( env_config )::get
(.cntxt(this),.inst_name(""),.field_name("h_env_cnfg"),.value(h_env_cnfg)))
begin
`uvm_fatal( get_name(), "h_env_cnfg not found" )
end
//ASSIGN THE AGENT-CONFIG FROM ENV-CONFIGURATION
uvm_config_db#( agent_config )::set
(.cntxt( this ),.inst_name("h_agt*"),.field_name("h_agt_cnfg"),.value(h_env_cnfg.h_agt_cnfg));
h_agt = agent ::type_id::create("h_agt ",this);
h_predictor = reg_predictor ::type_id::create("h_predictor",this);
`uvm_info(get_full_name()," AGENT CREATION DUE TO SWITCH", UVM_DEBUG);
`uvm_info(get_type_name(),"build",UVM_DEBUG);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(h_env_cnfg.h_reg_block.get_parent() == null)
begin
h_env_cnfg.h_reg_block.reg_map.set_sequencer(.sequencer( h_agt.h_seqr ),.adapter( h_agt.h_adapter));
end
h_env_cnfg.h_reg_block.reg_map.set_auto_predict(.on(0));
h_predictor.map = h_env_cnfg.h_reg_block.reg_map;
h_predictor.adapter = h_agt.h_adapter;
h_agt.AP_in_agt.connect(h_predictor.bus_in);
`uvm_info(get_type_name(),"connect",UVM_DEBUG);
endfunction : connect_phase
endclass : my_env
----------------[test]--------------------
class my_reg_test extends my_test_base;
`uvm_component_utils(my_reg_test)
//REGISTER MODEL
uvm_reg_map reg_map;
my_reg_block reg_block;
string reg_name;
bit[15:0] reg_data;
bit[15:0] read_data;
bit[15:0] rst_data;
uvm_status_e op_status;
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction : new
task run_phase(uvm_phase phase);
seq = my_sequence ::type_id::create("seq ");
rst = assert_rst ::type_id::create("rst");
phase.raise_objection(this,"test starts now");
h_env.h_env_cnfg.h_reg_block.STATUS_CONTROL_REG.RAJ.set(3'h7);
h_env.h_env_cnfg.h_reg_block.STATUS_CONTROL_REG.update(op_status, .path(UVM_FRONTDOOR), .map(reg_map), .parent(null));
repeat(10) @(posedge v_if.clk); //some delay before read
h_env.h_env_cnfg.h_reg_block.STATUS_CONTROL_REG.RAJ.predict(3'h7);
h_env.h_env_cnfg.h_reg_block.STATUS_CONTROL_REG.RAJ.mirror(op_status, .check(UVM_CHECK), .path(UVM_FRONTDOOR), .map(reg_map), .parent(null));
phase.drop_objection(this,"test ends now");
endtask : run_phase
endclass : my_reg_test
-----------------[ monitor ]-------------------
task run_phase(uvm_phase phase);
@(posedge v_if.clk);
begin
@(posedge v_if.o_data_vld);
begin
uvm_info(get_type_name(), $sformatf("o_data_vld :: %0d, o_rd_data :: %0d",v_if.o_data_vld,v_if.o_rd_data),UVM_LOW) my_txn.rd_addr = v_if.i_rd_addr; AP_mon.write(my_txn); uvm_info(get_type_name(),“sampled vld data”,UVM_LOW)
end
end
endtask : run_phase
-----------------[ log ]-------------------
UVM_INFO @ 0: reporter [RNTST] Running test my_reg_test…
UVM_ERROR verilog_src/uvm-1.0p1/src/reg/uvm_reg.svh(2892) @ 255: reporter [RegModel] Register “STATUS_CONTROL_REG” value read from DUT (0x0000000000000000) does not match mirrored value (0x0000000000000007)
UVM_INFO verilog_src/uvm-1.0p1/src/reg/uvm_reg.svh(2902) @ 255: reporter [RegMem] field RAJ mismatch read=3’h0 mirrored=3’h7 slice [2:0]
UVM_INFO …/tb/agent/monitor.svh(64) @ 265: uvm_test_top.h_env.h_agt .h_mntr [monitor] o_data_vld :: 1, o_rd_data :: 7
UVM_INFO …/tb/agent/monitor.svh(67) @ 265: uvm_test_top.h_env.h_agt .h_mntr [monitor] sampled vld data
UVM_INFO verilog_src/uvm-1.0p1/src/base/uvm_objection.svh(1116) @ 1255: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase
**
Please help me in resolving this issue.**
Thank you,
Regards,
Tejas T V