Problem with constructing UART reg model

Hi.

I have a question about Uart register model

In spec, The uart registers THR, RBR and Divisor-Latch(LSB) share the same address in device.

THR is write-only, RBR is read-only and Divisor latch is RW. The access between THR/RBR and Divisor is controlled by LCR[7] (Line control register)

I think they are combination of Lock register model and sharing address model in UVM user guide.

How can i implement the register model of this??

Thanks