The uvm_reg::do_predict() method seems to not properly predict when there's a write access to a portion of the register's field.
Seems that UVM assumes that the entire field is either byte_enabled or not byte_enabled, and it decides that only by the LSB of the reg_field.
For example, I got a write access to a 64-bit register, only to the 2nd byte (i.e, byte_enable=0x2), and the register has a field called ADDR within bits 52:7.
What happens is UVM decides the entire ADDR field is not byte_enabled since the 7th bit belongs to the 1st byte, which is indeed not byte_enabled, and so it does not predict bits 15:8 (2nd byte that was accessed) as it should have.
Has anyone bumped into this UVM issue and perhaps know how to bypass/fix that?