The code from “Practical Guid to Adopting the Universal Verification Methodology(UVM)” by
Rosenberg and Meade:
// Compile the UVM package
`include “uvm_pkg.sv”
module hello_world_example();
// Import the UVM library and include the UVM macros
import uvm_pkg::*;
include "uvm_macros.svh" initial begin
uvm_info(“info1”,“Hello World!”, UVM_LOW)
end
endmodule: hello_world_example
Compiled in Questasim via:
doHello
set MTI_HOME c:/questasim64_10.0c
set UVM_HOME $MTI_HOME/verilog_src/uvm-1.1
setenv MTI_HOME c:/questasim64_10.0c
setenv UVM_HOME $MTI_HOME/verilog_src/uvm-1.1
vlog -64 c:/questasim64_10.0c/verilog_src/uvm-1.1/src/uvm_pkg.sv
vlog -64 hello.sv
When I attemp to simulate this example:
vsim hello_world_example
vsim hello_world_example
** Fatal: (vsim-7019) Can’t locate a C compiler for compilation of DPI export tasks/functions.
Time: 0 ns Iteration: 0 Unknown: File: UNKNOWN
FATAL ERROR while loading design
Error loading design
I have visual C++ Express. Why isn’t Mentor using that?