Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
UVM
  • Home
  • Forums
  • UVM
  • post_randomization block is not executing

post_randomization block is not executing

UVM 5577
pre_randomize &... 1
jd_jagdish
jd_jagdish
Full Access
4 posts
January 19, 2021 at 4:25 am

Hay!
I have used a post_randomize function in my sequence_item class.
Also I have used for loop, while loop, if statements inside it
i am using .randomize() inside a task in sequence class.
when i am running the post_randomize() function is not executing.
plz help me out this.

Replies

Log In to Reply
chr_sue
chr_sue
Full Access
3254 posts
January 19, 2021 at 8:04 am

In reply to jd_jagdish:

Could you please show your sequence body task and the definition of the seq_item.

dave_59
dave_59
Forum Moderator
8574 posts
January 19, 2021 at 11:53 am

In reply to jd_jagdish:

Did you check the return value from the call to randomize()? post_randomize() does not get called if the solver fails.

— Dave Rich, Verification Architect, Siemens EDA

jd_jagdish
jd_jagdish
Full Access
4 posts
January 19, 2021 at 7:47 pm

In reply to chr_sue:

This is my code 

//sequence_item class 
 
class packet extends uvm_sequence_item;
 
//input signal that can be randomize
rand 	bit start_1;
rand 	bit ble;
rand 	bit cca;
 
// output logic signal that should not be randomize
logic result;
 
`uvm_object_utils_begin(packet)
	`uvm_field_int(start_1,UVM_ALL_ON|UVM_DEC)
	`uvm_field_int(ble,UVM_ALL_ON|UVM_DEC)
	`uvm_field_int(cca,UVM_ALL_ON|UVM_DEC)
`uvm_object_utils_end
 
 
 
int cnt=0;
bit count=0;
constraint valid{
 
	//start inside {[0:1]};
		cca inside {[0:1]};
		ble inside {[0:1]};
}
 
function void post_randomization();
 
while(cnt<4)
	begin
		if (count==1)
			begin	
				start_1=1;
				cca=0;
				ble=0;
				count=~count;
			end
		else
			begin
				start_1=0;
				cca=0;
				ble=0;
				count=~count;		
			end
	cnt=cnt+1;
	end
if(cnt==4)
	begin
		count=1;
		cnt=cnt+1;
	end
else if(cnt>4)
 
			begin
				cca=1;
				ble=1;
 
			end
 
		else
			begin
				cca=1;
				ble=0;
			end
	end
 
endfunction
 
function new (string name="packet");
super.new(name);
endfunction
 
endclass:packet
 
 
//sequence class
 
class packet_sequence extends uvm_sequence#(packet);
	`uvm_object_utils(packet_sequence)
 
	bit start_1;
	bit ble;
	bit cca;
 
	function new (string name="packet_sequence");
		super.new(name);
	endfunction
 
task body();
 
	packet ref_pkt;
	ref_pkt=packet::type_id::create("ref_pkt");
	repeat(50)
	begin
	`uvm_create(req)
		assert(ref_pkt.randomize with {ref_pkt.start_1==0;ref_pkt.ble==0;ref_pkt.cca==0;});
 
		req.copy(ref_pkt);
		start_1=req.start_1;
		cca=req.cca;
		ble=req.ble;
		start_item(req);
		req.print(uvm_default_line_printer);
		finish_item(req);
 
 
	`uvm_create(req)
		assert(ref_pkt.randomize with {ref_pkt.start_1==1;ref_pkt.ble==0;ref_pkt.cca==1;});
		req.copy(ref_pkt);
		start_1=req.start_1;
		cca=req.cca;
		ble=req.ble;
		start_item(req);
		req.print(uvm_default_line_printer);
		finish_item(req);
 
		end	
endtask		
endclass:packet_sequence
jd_jagdish
jd_jagdish
Full Access
4 posts
January 19, 2021 at 7:50 pm

In reply to dave_59:

should i need to use return after .randomize() in body of sequence class?

chr_sue
chr_sue
Full Access
3254 posts
January 19, 2021 at 11:23 pm

In reply to jd_jagdish:

2 things:
(1) do you see the diagnostic messages (print) in your log-file?
(2) why you are using a copy (req) of your original data packet (ref_pkt)?

jd_jagdish
jd_jagdish
Full Access
4 posts
January 20, 2021 at 2:54 am

In reply to chr_sue:

yes i am getting the print messages in log file.
The "req" that i have used is not required. I simply used to check what's happening.

chr_sue
chr_sue
Full Access
3254 posts
January 20, 2021 at 4:26 am

In reply to jd_jagdish:

If you see the print messages from post_randomize it will be definitely executed.
I gues you are getting in the driver the ref_pkt instead of req.

Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy