Phase objection

UVM
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1

Hi,

I want to know from where i need to raise an objection.

I initially put raise/drop objection in the sequence and i found that to be working.
I found few examples where people have raised/dropped objection in testcase.

I tried to do the same, but my testcase ended without even randomizing the set of sequence items.

Please explain.

Thanks

2

Hi Debjit

Please add option +UVM_OBJECTION_TRACE in vsim. It is very helpful to debug.

vsim +UVM_TESTNAME=uart_sequence_test +UVM_VERBOSITY=UVM_HIGH
+UVM_OBJECTION_TRACE
-l tt.log
-f questa.tops
-sv_lib uvm_dpi

#log

UVM_INFO ./examples/./test_lib.sv(50) @ 0: uvm_test_top [uart_sequence_test] $time

UVM_INFO ./sv/./uart_monitor.sv(127) @ 0: uvm_test_top.demo_tb0.uart0.Tx.monitor [uart_tx_monitor] Start Running

UVM_INFO ./sv/./uart_monitor.sv(127) @ 0: uvm_test_top.demo_tb0.uart0.Rx.monitor [uart_rx_monitor] Start Running

UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq raised 1 objection(s) (Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=1 total=1

UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx.sequencer added 1 objection(s) to its total (raised from source object , Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=0 total=1

UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top.demo_tb0.uart0.Tx added 1 objection(s) to its total (raised from source object , Running sequence ‘uvm_test_top.demo_tb0.uart0.Tx.sequencer.uart_incr_payload_seq’): count=0 total=1

And there are some codes example uses raise_objection in main_phase of test in mentor uvm cook book.

task spi_test::main_phase(uvm_phase phase);
send_spi_char_seq spi_char_seq = send_spi_char_seq::type_id::create(“spi_char_seq”);
phase.raise_objection(this, “starting spi_char_seq in main phase”);
spi_char_seq.start(m_env.m_v_sqr.apb);
#100ns;
phase.drop_objection(this, “finished send_spi_char_seq in main phase”);
endtask: main_phase

Regards,
Yao he

3

In reply to yaohe:

Hi,

I will surely refer to the cookbook. I understand that objections can be raised from test, but my question is how to decide from where to raise the objection, whether from testcase, sequence or driver?

a) What factors dictate the point of raising an objection?

b) Can you suggest a scenario where raising an objection has to be done from testcase/driver and not from sequence?

c) Can you suggest a scenario where objections need to be raised from multiple places?

Thanks

4

In reply to Debjit:

Since the test controls which sequences are run() and knows when they are complete, objections should only be controlled in the test. There should never be a reason to control objections within a sequence since it is possible to terminate a running sequence which will result in an objection not being lowered properly.

5

In reply to cgales:

Hi,
Thanks for that reply.
It answers my queries.

I still have one basic doubt.
Can there be a scenario where i will be required to raise multiple objections?

I have just started to learn UVM, hence i have this doubt.

Thanks.

6

In reply to cgales:

what is use of phase raise objecttion

7

In reply to Debjit:

In reply to cgales:
Hi,
Thanks for that reply.
It answers my queries.
I still have one basic doubt.
Can there be a scenario where i will be required to raise multiple objections?
I have just started to learn UVM, hence i have this doubt.
Thanks.

There are no general rules where you need more than 1 objection mechanism.