In reply to chr_sue:
so what I have
pe3rc_cfg_test - has pe3rc_cfg_seq where in body task regs are updated and then we wait for 1 bit to start other activity
pe3rc_cfg_test also extended from pe3rc_base_test where i have some randomization and setting components to uvm_config_db#
class pe3rc_int_test extends pe3rc_cfg_test;
...
uvm_config_db#(uvm_object_wrapper)::set(this, "env.pcie_agt[*].driver_transaction_seqr[0].main_phase", "default_sequence", pcie_int_seq::type_id::get()); // pcie_int_seq - generate interrupts
...
endclass : pe3rc_int_testthe main sequence here, i randomly generate asserts and deasserts, memorize it in tmp variable, then after main loop deasserting what haven't been deasserted
all things with svt_* is a from VIP environment from vendor
...
task body();
repeat (64) begin
// if(int_slot != 4'hf) begin
do_rand_again = 0;
do begin
req = svt_pcie_driver_app_transaction::type_id::create("req");
req.cfg = cfg;
req.reasonable_pkt_delay_ns.constraint_mode(1'b0);
req.randomize() with {
transaction_type == MSG;
routing_type == LOCAL;
message_code inside {ASSERT_INTA, ASSERT_INTB, ASSERT_INTC, ASSERT_INTD, DEASSERT_INTA, DEASSERT_INTB, DEASSERT_INTC, DEASSERT_INTD};
ep == 1'b0;
pkt_delay_ns inside {[600:2000]};
};
case(req.message_code)
svt_pcie_driver_app_transaction::ASSERT_INTA: begin
do_rand_again = int_slot[0] ? 1 : 0;
if(!do_rand_again) int_slot[0] = 1'b1;
end
....
endcase
`uvm_info(get_name(), $sformatf("try current code=%s when int_slot=b'%0b", req.message_code, int_slot), UVM_LOW)
end while (do_rand_again);
// end
`uvm_info(get_name(), req.sprint(uvm_default_line_printer), UVM_LOW)
start_item(req);
finish_item(req);
get_response(req);
#(req.pkt_delay_ns * 1ns);
end// repeat (64) begin
do_rand_again = 0;
while(int_slot != 0) begin
`uvm_info(get_name(), $sformatf("After test deasserting, current int_slot=b'%0b", int_slot), UVM_LOW)
do begin
req = svt_pcie_driver_app_transaction::type_id::create("req");
req.cfg = cfg;
req.randomize() with {
transaction_type == MSG;
routing_type == LOCAL;
message_code inside {DEASSERT_INTA, DEASSERT_INTB, DEASSERT_INTC, DEASSERT_INTD};
ep == 1'b0;
};
....
end while (do_rand_again);
`uvm_info(get_name(), req.sprint(uvm_default_line_printer), UVM_LOW)
start_item(req);
finish_item(req);
get_response(req);
#(req.pkt_delay_ns * 1ns);
end
endtask : body
endclass : pcie_int_seqUVM topology is a very long list, I don't know if I put in here would it be helpful or not
