Pass a parameter from uvm_test to uvm_sequence_item

I want to pass a parameter from uvm_test class to uvm_sequence_item class through the factory mechanism of set and get. I can pass parameters from uvm_test class to uvm_sequence class using p_sequencer. But what about passing parameters to uvm_sequemce_item class?

You should be using the config_db to pass parameters to the sequencer and retrieve them using m_sequencer in both the sequence and sequence_item. No need for p_sequencer.

In reply to dave_59:

Dave,

Can you post and example (or a pointer to the cookbook) where this method is used? I’d like to be developing more “configurable sequences” and want to understand the recommendations and best-practices.

Thanks,
Doug

In reply to dwikle:

Here is an even better suggestion: Config/ConfiguringSequences | Verification Academy

In reply to dave_59:

Hi Dave:

That’s the example how to control the sequence, not sequence_item. Is it there any way to pass parameter down to sequence item?

My case is I have a port from DUT that the width is parameterized (Can be any value from 8 to 32). Read some articles about the parameterized interface, but still haven’t get the idea and also the sequence item should be parameterized too. Is it there any good way to test it without hard coded every value of that parameter?

Thanks.

In reply to Enzo Chi:

It’s too expensive to have every sequence_item look up information in the config_db. Just have your sequence set a width variable in the sequence_item after it gets created, and declare the data width using the max width(32).

Thanks Dave.

I am not sure if anyone knows where can I find example code about parameterized interface.

Thanks

In reply to Enzo Chi:

Check the DVCon proceedings. There are one or two papers a year on this topic.