Pass delay from the testcase

UVM
1

Hi,

Is it possible to pass delay from the testcase as we pass other values?
For example i want to pass 10ns as delay from the testcase to the sequence.

2

In reply to shankar_logic:
Hi

If it is fixed delay, parameterized sequence can be used.
class test_seq#(parameter int DELAY= 10) extends uvm_sequence
…
Delay … //Update this parameter from test while creating sequence
…
endclass

If it is variable delay, it can be done as -
class test_seq extends uvm_sequence

rand time DELAY; //Assign this value from test as test_seq.DELAY = 10ns
… //OR
Delay … //It will be randomized once sequence randomization is called
…
endclass

3

In reply to shankar_logic:

It looks like you do not understand the mechanisms of TLM. The TLM does not know anything about time and timing. It works completely untimed. The only order scheme is the order of the data and commands/instructions.

4

Actually i don’t want to pass through TLM. I want to pass delay value in a form of parameter or through configuration database.

I was looking if there is some standard mechanism for that in UVM

5

Thanks for the solution.

6

But how to pass ns unit

7

In reply to shankar_logic:

There is no standard mechanism for passing delays in UVM because they should NEVER be used. As Christoph mentioned, UVM is TLM based. Being TLM based, sequences have no concept of time and there should NEVER be a Delay statement in a sequence.

There may be Delay statements in drivers, but ideally they should be clock-based delays.

8

But in virtual sequence, if i want to add delay between two sequences and this delay is variable then how to control it through the testcase.

9

In reply to shankar_logic:

Again, the sequence execution happens on the TL and this level does not know anything about time and timing. Only the transactors (blocks connected to the virtual interface) deal with the timing. You can control the sequence execution from there, i.e. by calling get/get_next:iem with a certain delay (exactly what cgales is saying).

10

In reply to chr_sue:

In reply to shankar_logic:
Again, the sequence execution happens on the TL and this level does not know anything about time and timing. Only the transactors (blocks connected to the virtual interface) deal with the timing. You can control the sequence execution from there, i.e. by calling get/get_next:iem with a certain delay (exactly what cgales is saying).

Ok Thanks