Parent and this argument

UVM
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1

Hello,

I have two different questions.

  1. In some function passes an argument “this” or “Parent” words. What does it mean? And when we have to pass those arguments?
    Below is one example:
class my_env extends uvm_env;
  inp_agent my_agt;
   virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    my_agt = inp_agent::type_id::create("my_agt", this);
  endfunction
endclass

What is the reason to give “this” argument to create the function?

Can someone explain it with details? It will be very helpful. Also, I can give another example from verification academy video courses.

  1. I find out there is “set_automatic_objection()” macro. It is compatible with uvm1.1 or it only works with uvm1.2?

Thank you

2

In reply to meruzha:

You are building the testbench hierarchy. The hierarchy gets used for building reference names and also traversing all the components in your testbench. Please see my short course on SystemVerilog OOP if you don’t understand what the this keyword means.

The set_automatic_phase_objection() method was introduced in UVM 1.2 and is not backward compatible. We recommend raising/dropping objections in your test instead of constantly doing that as you execute each sequence.