Parameterized Interface passing through config_db

HI All,

I have interface lets say

interface intf #(N=8);
      logic [N-1 : 0] data;
      logic [N-1 : 0] addr;
   endinterface

In build_phase of test, Iam randomizing N value and parameterising Interface with the randomized N value, and setting it to lower components through uvm_cobfig_db.

When I get it, I do not know what is the randomized N value in test for instantiating it. If I try to get with default value, its a compatible error. How to get the parameterised interface in this case?   Please help me out

In reply to Anudeep J:

You cannot randomize the value of a parameter because parameter values are set as part of the compilation and elaboration process before simulation starts.

What you can do is randomize N is a separate simulation run, and use that value to set the parameter override in your UVM testbench simulation.

Another option is to forget about randomizing the widths of data and addr and just declare them with a maximum width.

In reply to dave_59:

THanks Dave,

This is fine. My actual intention is, I want to set a parameterized interface from test and get that in driver component. The parameter can be anything. But Iam unaware of it in the driver component. So How do I instantiate my interface and get it properly in the driver?

In reply to Anudeep J:
You pass a parameterized interface instance through the uvm_config_db the same way you pass an unparameterized interface.

// in top module 
 uvm_config_db#(intf#(N))::set(null, "*", "intf", intf_inst);

// in driver class
class driver;

virtual intf#(N) v_intf;
...
if (!uvm_config_db #(intf#(N)))::get(this, "", "", v_intf)) // get config 


The problem is N has to be set with the same value at compilation. You get get N from a common package by everywhere replacing N with my_params::N

package my_params;
parameter N = 5;
endpackage

In reply to dave_59:

Hi Dave,

what about if I have to instantiate two different instances (with different value of N) of the same virtual interface?

// in top module
uvm_config_db#(intf#(M))::set(null, “", “intf”, intf_inst_1);
uvm_config_db#(intf#(N))::set(null, "
”, “intf”, intf_inst_2);

I suppose that first set db creates an interface with M, while the second config_db returns an error because it finds a interface already set with M.

Am I wrong?