Packet generating

UVM
,
1

I’m generating one packet in driver this


	 @(posedge vif.clk)
	  vif.source_cb.sop   <= 1;
	  vif.source_cb.data  <= trans.data;
	  vif.source_cb.valid <= 1;
	  vif.source_cb.eop   <= 1;

And I repeated this packet 20 times inside sequence

virtual task body();
 
    trans = a_sequence_item::type_id::create("trans");
   
    repeat(20) begin
	  `uvm_info(get_type_name(), "Executing sequence", UVM_LOW)
       start_item(trans);
       assert(trans.randomize());
       finish_item(trans);
	   //`uvm_do(trans)
    end
   endtask
2

In reply to UvmSv:

Then you have to instruct your sequence to do that explicitly using constraints.

assert(trans.randomize()with {sop == 1; eop == 0;});
3

In reply to chr_sue:

assert(trans.randomize()with {sop == 1; eop == 0;});
assert(trans.randomize()with {sop == 0; eop == 0;});
assert(trans.randomize()with {sop == 0; eop == 1;});

This way…

4

In reply to UvmSv:

Yes using inline constraints.