Overwriting Assign statement

I have an assignment statement that assigns an enum variable of type logic defined in an interface in my top module, when I overwrite this variable in the body task of my sequence (which is supposed to be a procedural code) there is no compilation error and the variable is overwritten until it is assigned a new value that overwrites it again, so my question is how is this allowed?

In reply to Abdelrahman Adel:
Please show the related code. This gives us a chance help you.


  interface ALU_in_if; 
  logic clk;
  logic rst;
  logic[2:0] temp;
endinterface


module UVM_Top;
  ALU_in_if my_ALU_in_if();
  assign #5 my_ALU_in_if.temp = my_ALU_in_if.temp + 1; //the assign statement
  initial begin
  end
endmodule

//In UVM driver 
virtual ALU_in_if mydriver_ALU_in_if;
uvm_config_db#(virtual ALU_in_if)::get(this,"","ALU_in_vif",mydriver_ALU_in_if)
task run_phase(uvm_phase phase);
  super.run_phase(phase);
  mydriver_ALU_in_if.temp = 5; //overwriting the assign statement
  $display("TEMP = %0d",mydriver_ALU_in_if.temp); 
endtask

How is it possible to overwrite the assign statement inside a procedural code?

In reply to Abdelrahman Adel:

This code is illegal and should’ve produced an error. You cannot mix procedural and continuous assignments to the same variable. In this case, the continuous assignment has a feedback loop with a delay making it easy to predict when the continuous assignment reapplies. But without that feedback loop, it depends on when the RHS has an updated value before the LHS gets updated.

When trying this code with a number of simulators on EDAPlayground, it seems that none of the tools produce an error because of the virtual interface indirection.