Overriding uvm_transaction with other different uvm_transaction

UVM
1

Hi,

I would like to pass two different transactions with in a single put port like the following;

class componentA extends uvm_component;
uvm_blocking_put_port#(trans1) item_port;
trans1 item;
…
task run_phase(uvm_phase phase);
forever begin
item_port.put(item);
end
endtask
endclass
I would like to override trans1 to trans2(completely different one). Can anybody suggest me; Is there any way to do it?

thanks,
mahee.

2

Provided trans2 inherits from trans1, then you can do this in any case as a result of polymorphism - i.e. you can send both trans1 and trans2 types via the port.

You can also do a UVM factory type override for trans2 with trans1.