Overriding one (object) class with another in the test using set_type_override_by_type

UVM
1

I tried to override a extended packet i.e “dll_packet”
the code for packet and dll packet is shown below

class packet extends uvm_sequence_item ;
rand bit[7:0]datain_a,datain_b;
rand bit [1:0] control_in_a,control_in_b;
bit [1:0] control_out_a,control_out_b;

       bit header_start_a,header_start_b;
       bit header_end_a,header_end_b;
bit [7:0] dataout_a,dataout_b;

uvm_object_utils_begin(packet) uvm_field_int(datain_a,UVM_ALL_ON)
uvm_field_int(datain_b,UVM_ALL_ON) uvm_field_int(control_in_a,UVM_ALL_ON)
uvm_field_int(control_in_b,UVM_ALL_ON) uvm_field_int(control_out_a,UVM_ALL_ON)
uvm_field_int(control_out_b,UVM_ALL_ON) uvm_field_int(header_start_a,UVM_ALL_ON)
uvm_field_int(header_start_b,UVM_ALL_ON) uvm_field_int(header_end_a,UVM_ALL_ON)
uvm_field_int(header_end_b,UVM_ALL_ON) uvm_field_int(dataout_a,UVM_ALL_ON)
uvm_field_int(dataout_b,UVM_ALL_ON) uvm_object_utils_end

function new (string name=“packet”);
super.new(name);
//`uvm_info(“PACKET”,$sformatf(“%m”),UVM_HIGH);
endfunction

constraint control_a_c{control_in_a == 1 || control_in_a==2 ;} ;
endclass

class dll_packet extends packet;
`uvm_object_utils(dll_packet)

function new (string name=“dll_packet”);
super.new(name);
//`uvm_info(“PACKET”,$sformatf(“%m”),UVM_HIGH);
endfunction

constraint dllp_a {control_in_a==1 ;};
constraint dllp_b {control_in_b==1 ;};
endclass

tried to override in extended dll_packet_test
the code for base test and dll_packet_test is shown below

class test_base extends uvm_test;
`uvm_component_utils(test_base)

environment env;
function new(string name, uvm_component parent);
super.new(name, parent);
`uvm_info(“TRACE”, $sformatf(“%m”), UVM_HIGH);
endfunction

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_info("TRACE", $sformatf("%m"), UVM_HIGH); uvm_info(“TRACE”, $sformatf(“build phase in test base”), UVM_HIGH);
env = environment::type_id::create(“env”, this);
// uvm_config_db#(virtual phy_tx_intf )::set(this,““,“pcie_phy_if”,test_top.bus);
uvm_config_db#(virtual phy_tx_intf )::set(this,””,“phy_tx_intf”,test_top.bus);
uvm_config_db#(virtual phy_tx_intf1 )::set(this,“*”,“phy_tx_intf1”,test_top.bus1);
endfunction

virtual function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
`uvm_info(“TRACE”, $sformatf(“%m”), UVM_HIGH);
uvm_top.print_topology();

factory.print();

endfunction
endclass

class dll_packet_test extends test_base;
`uvm_component_utils(dll_packet_test)

function new(string name, uvm_component parent);
super.new(name, parent);
`uvm_info(“TRACE”, $sformatf(“%m”), UVM_HIGH);
endfunction

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info(“TRACE”, $sformatf(“%m”), UVM_HIGH);

`uvm_info("TRACE", $sformatf("build phase in dll test"), UVM_HIGH);

set_type_override_by_type(packet::get_type(),dll_packet::get_type());

endfunction
endclass

in synopsys VCS

it is not overriding the packet with dll_packet

the message i got using factroy.print()
is

Factory Configuration (*)

No instance or type overrides are registered with this factory
it showing

2

In reply to Sameer Mohammad:

Two things:
(1) Calling the override in the build_phase is not the right place. Instead do it in the end_elaboration or the start_simulation_phase. The seq_item does not belong to the topology.
(2) set_type_override_by_type has to be called on a factory object.