I meet a error that "NULL pointer dereference" when simulation. The error occurs when calling the interface.
1. I create a interface :
interface adiv_if ();
bit clk_target;
bit clk;
assign clk = adiv_block_tb_sim_top.dut.clk;
assign clk_target = adiv_block_tb_sim_top.dut.u_adiv_core.clk_target;
endinterface
2. I instantiate in sim_top, and set * use config_db
`include "adiv_if.sv"
module adiv_block_tb_sim_top;
virtual adiv_if aif;
//....
uvm_config_db#(virtual adiv_if)::set(null, "*", "aif", aif);
//....
endmodule
3. I get interface(aif) in the base_test
[systemverilog]
virtual class adiv_block_tb_base_test extends uvm_test;
virtual adiv_if aif;
//...
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual adiv_if)::get(this, "", "aif", aif))
`uvm_fatal(get_full_name(),"not get adiv_if");
endfunction : build_phase
//...
endclass4. I create a testcase extends base_test
class adiv_block_tb_verilog_test extends adiv_block_tb_base_test;
//...
virtual task main_phase(uvm_phase phase);
$display("get adiv_if clk_target is %0d",aif.clk_target); //(line44)
endtask
//...
endclassI completed above code, the error occurs when simulation
//======error message=========
get adiv_if xmsim: *E,TRNULLID: NULL pointer dereference.
File: /home/yguo3/adiv/adiv_blk_env/adiv_block_tb/tests/adiv_block_tb_verilog_test/adiv_block_tb_verilog_test.sv, line = 44, pos = 34
Scope: worklib.adiv_block_tb_env_pkg::adiv_block_tb_verilog_test@4769_1.build_phase
Time: 0 FS + 6
Verilog Stack Trace:
0: function worklib.adiv_block_tb_env_pkg::adiv_block_tb_verilog_test@4769_1.build_phase at /home/yguo3/adiv/adiv_blk_env/adiv_block_tb/tests/adiv_block_tb_verilog_test/adiv_block_tb_verilog_test.sv:44
1: function worklib.uvm_pkg::uvm_build_phase@2981_2.exec_func at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_common_phases.svh:54
2: function worklib.uvm_pkg::uvm_topdown_phase@2981_2.execute at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_topdown_phase.svh:111
3: function worklib.uvm_pkg::uvm_topdown_phase@2981_2.traverse at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_topdown_phase.svh:78
4: function worklib.uvm_pkg::uvm_topdown_phase@2981_2.traverse at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_topdown_phase.svh:95
5: task worklib.uvm_pkg::uvm_phase@3011_2.execute_phase at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_phase.svh:1168
6: process in worklib.uvm_pkg::uvm_phase::m_iterate_through_phases at /cad/adi/apps/cadence/xlm/linux/20.09-s09/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_phase.svh:1997
/home/yguo3/adiv/adiv_blk_env/adiv_block_tb/tests/adiv_block_tb_verilog_test/adiv_block_tb_verilog_test.sv:44 $display("get adiv_if %d",aif.clk_target);
xcelium> exit
//=============
error line44 : $display("get adiv_if clk_target is %0d",aif.clk_target);
May I ask what is causing this problem and how to fix it? Thinks very much!
