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  • Not able to define a function in interface and call it from Class

Not able to define a function in interface and call it from Class

UVM 7028
calling a function... 1
Sank
Sank
Full Access
2 posts
November 22, 2022 at 2:37 am

Hi,

Below is what I am trying.

I have defined a function in an interface definition. Have instantiated the interface and set interface handle to config_db.

I am trying to call this function inside a Class method, via the virtual interface handle got from the config_db.

Please guide if this construct is allowed in SV/UVM. Also, what could be the possible mistake I am making here..

Below is how the error looks:

Error-[MFNF] Member not found
/asic/users/xyz/axon/tb/comps/sram_monitor/sram_monitor.sv, 191
"this.m_ctest_mon_tmp_interface."
Could not find member 'get_mem_value' in interface
'ctest_mon_tmp_interface', at
"/asic/users/xyz/axon/tb/comps/ctest_sram_monitor/ifc/ctest_mon_tmp_interface.sv",
7.
Instance stack trace:
ctest_sram_monitor#("CORE3")
/asic/users/xyz/axon/tb/comps/env.svh, 83
env_pkg
/asic/users/xyz/axon/tb/comps/env_pkg.sv, 7

Thanks,
San

Replies

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ABD_91
ABD_91
Forum Access
206 posts
November 22, 2022 at 3:21 am

In reply to Sank:

Please share some code ( mainly covering config_db::set , config_db::get and Tb hierarchy for sram_monitor )
You could also share a link to the complete code on edaplyaground

Sank
Sank
Full Access
2 posts
November 22, 2022 at 10:33 pm

In reply to ABD_91:

Hi,

Thanks to respond. Actually, I was making a mistake with compiling wrong file, not able to resolve the error and progress.

In same context, I am unable to use `uvm_info inside the interface code. Any guidance here?

I am compiling this xyz_interface.sv as a standalone file in test bench compilation file list. Tried adding the below two lines at start of file, but that did not help.

import uvm_pkg::*
`include "uvm_macros.svh"

Thanks,
San

dave_59
dave_59
Forum Moderator
11444 posts
November 24, 2022 at 5:48 am

In reply to Sank:

Can you show us your usage of `uvm_info and give us the error message you get?

— Dave Rich, Verification Architect, Siemens EDA

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