Can anybody explain the need of writing super.build_phase.
And is it necessary to write in all build_phase methods.
We recommended using the build_phase instead of putting any code inside the constructor method new(). You can choose to call super.build_phase() in an extended class depending on whether you want to completely override or add the the existing functionality in the base class build_phase()
You can’t completely override a constructor because SystemVerilog requires that the extended class constructor call super.new() as the very first statement.
You only need super.build() in your base class’s build_phase if you are using the field automation macros for them do their magic. We strongly discourage the use of field automation macros because of their performance overhead.
In reply to dave_59:
Hi Dave,
How super.build_phase() is going to help the field registration macros to do their work??
I guess, the methods in uvm_object like do_copy, do_compare and other methods will be working on the properties which are registered to the factory using macros… What is the link between these macros and super.build_phase??? Can you please elaborate it???
Don’t misunderstand that I am using those macros because, I am far more aware of the fact that field registration macros are not recommended by Mentor Graphics since they are hard to debug and they put on heavy overhead on the simulator and thus reducing the performance of the simulator.
In reply to puttasatish:
The factory and field automation are independent features. It’s just that the uvm_component_utils_begin macro adds the code for both. The uvm_component_utils macro just adds the factory registration code. There is no documented macro that just adds field automation, although if you look at the source code, you could easily figure it out.
The uvm_component::build_phase() method calls uvm_component::apply_config_settings().
Searches for all config settings matching this component’s instance path. For each match, the appropriate set_local method is called using the matching config setting’s field_name and value. Provided the set_local method is implemented, the component property associated with the field_name is assigned the given value.
In addition to the overhead of searching through the config db, many users are unaware of the difference in this behavior between uvm_components versus uvm_objects. There are also unaware of which types have the set_*_local methods defined.
In reply to dave_59:
Hi Dave,
Actually i am a newbie to UVM. I am confused in where to use new() and where to use build phase? Can you please help me out?
In reply to Ayush:
The UVM is a phased approach. You have certain phases which are executes in a well-defined order. In the build_phase all components of your UVM testbenbch will be constructed. This goes topdown. In the connect_phase all components will be connected. This goes bottom-up. new() is the constructor whic is needed by each class. Ther4 is no new_phase in the UVM.
In reply to Ayush:
Ayush,
You should be looking at the basic UVM courses on this site. When you define a class derived from uvm_component, you declare both new() and build_phase() methods. I described above what code goes in each.
In reply to dave_59:
Thanks Dave,
Actually i am confused in that whether can we create constructor for the class which is being extended from uvm_component in build phase,rather than calling new for creating constructor?
In reply to Ayush:
I’m confused about what you are asking. Can you ask a new question and show some code on what you think you need to write versus what you want to write.
Hi Dave,
I have a
base_test extends uvm_test
and
test1 extends base_test
- If I don’t declare/define build_phase in test1, the base_test’s build_phase is called/executed automatically
- If I declare/define buil_phase in test1, and call super.build_phase() here, the base_test’s build_phase is called/executed again after the above automatic call/execution?
- What is the difference between the two above?
- How can I completely override base_class’s build_phase, as it is automatically called in uvm? This is required if I need to completely override a common register config from base_test to test1.
-mpattaje
In reply to mpattaje:
The UVM calls the virtual method build_phase(), and that call behaves like any other SystemVerilog virtual method—it calls the most derived declaration of that virtual method.
The class uvm_component declares virtual methods for all the ~25 UVM phases and calls them unconditionally. For each instance of a uvm_component (test1 would be one such instance) the most derived version of each phase gets called. So if there is a test1::build_phase, that is what gets called. If it doesn’t, it looks for base_test::build_phase. If that doesn’t exist, the uvm_component::build_phase gets called.
If you do not call super.method_name, no other method_name in the class inheritance tree gets called automatically. So without super.build_phase in test1::build_phase, base_test::build_phase does not get called. And if base_test::build_phase does not call super.build_phase, then uvm_component::build_phase will not get called either. Note that there is no uvm_test::build_phase. The keyword super means look back in the inheritance tree for the closest override.
In reply to dave_59:
In reply to mpattaje:
If you do not call super.method_name, no other method_name in the class inheritance tree gets called automatically. So without super.build_phase in test1::build_phase, base_test::build_phase does not get called. And if base_test::build_phase calls super.build_phase, then uvm_component::build_phase will not get called either. Note that there is no uvm_test::build_phase. The keyword super means look back in the inheritance tree for the closest override.
In the above statement, did you mean - And if base_test::build_phase DOES NOT call super.build_phase, then the uvm_component::build_phase will not get called either ?