Hi,
My test cannot start 2 sequence at the same time (only one sequence cxsccb_seq). I don’t understand why. I try to print from cxsccb_cre but nothing show up. Thank you.
My sequence code :
class cxsccb_cre extends uvm_sequence#(cxsb_trans_c);
`uvm_object_utils(cxsccb_cre)
cxsb_trans_c trans;
function new(string name = “cxsccb_cre”);
super.new(name);
endfunction
virtual task body();
repeat (1) begin
trans = cxsb_trans_c::type_id::create(“trans”);
`uvm_info(“SEQ”,$sformatf(“trans”),UVM_NONE);
wait_for_grant();
//trans.randomize();
trans.flit.Data = 2;
$display(“My trans in cre %p”, trans);
$display(“My flit in cre %p”, trans.flit);
send_request(trans);
wait_for_item_done();
end
endtask
endclass
class cxsccb_seq extends uvm_sequence#(cxsb_trans_c);
`uvm_object_utils(cxsccb_seq)
cxsb_trans_c trans;
function new(string name = “cxsccb_seq”);
super.new(name);
endfunction
virtual task body();
repeat (1) begin
trans = cxsb_trans_c::type_id::create(“trans”);
`uvm_info(“SEQ”,$sformatf(“trans”),UVM_NONE);
wait_for_grant();
trans.randomize();
$display(“My trans in seq %p”, trans);
$display(“My flit in seq %p”, trans.flit);
send_request(trans);
wait_for_item_done();
end
endtask
endclass
My test code:
class cxsccb_base_test extends acxl_base_test;
`uvm_component_utils(cxsccb_base_test)
cxsccb_env env;
cxsccb_seq seq;
cxsccb_cre cre;
function new(string name , uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
string name;
super.build_phase(phase);
env = cxsccb_env::type_id::create(“env”,this);
seq = cxsccb_seq::type_id::create(“seq”);
cre = cxsccb_cre::type_id::create(“cre”);
endfunction : build_phase
virtual function void end_of_elboration_phase(uvm_phase phase);
uvm_top.print_topology();
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
seq.start(env.agt.m_tx.m_sqr);//
cre.start(env.m_sqr_rx);
#10ns;
phase.drop_objection(this);
endtask : run_phase
endclass
My environment code:
class cxsccb_env extends uvm_env;
`uvm_component_utils(cxsccb_env)
cxsb_agent agt;
cxsccb_scb scb;
cxsb_sqr m_sqr_rx;
string if_path;
virtual cxsb_txrx_full_if vif;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if_path = “pcie_iod_tb.m_cxsb_txrx_if1.u_if”;
if(!uvm_config_db#(virtual cxsb_txrx_full_if)::get(null , “”, if_path, vif))
`vvm_fatal(“NO_VIF”,{“virtual interface must be set for:”,
get_full_name(),“.vif”});
agt = cxsb_agent::type_id::create(“agt”,this);
agt.set_intf(this.vif);
scb = cxsccb_scb::type_id::create(“scb”,this);
m_sqr_rx = cxsb_sqr::type_id::create(“m_sqr_rx”,this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
$display(“env connect phase is starting”);
agt.m_tx_mon.m_default_ap.connect(scb.m_tx_p);
agt.m_rx_mon.m_default_ap.connect(scb.m_rx_p);
agt.m_rx.seq_item_port.connect(m_sqr_rx.seq_item_export);
agt.m_rx.rsp_port.connect(m_sqr_rx.rsp_export);
endfunction
endclass
My sequencer code
class cxsb_sqr extends uvm_sequencer#(cxsb_trans_c);
`uvm_sequencer_utils(cxsb_sqr)
function new(string name = “cxsb_sqr”, uvm_component parent=null);
super.new(name, parent);
endfunction : new
endclass : cxsb_sqr