My RTL has top hierarchies in verilog and bottom level hierarchies in vhdl and the test bench is UVM based. I want to force a vhdl signal from my test to 0 for sometime?

I did the following tries and got the errors as below,
Try 1) The vhdl hierarchy signal is usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX which is a out,
From my test i did the following,

module 
initial run_test(usb_power_en_write_burst);

initial
begin
  ]usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX <= force out '1b0; //<-
#19680ns;
  usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX <= release; //<-
end
endmodule

I got errors as Following verilog source has syntax error, token is force

Try 2)

module 
initial run_test(usb_power_en_write_burst);

reg line_index=1b'0;
reg line_index_wire;
reg line_index_initial;
string  mem_vhdl_out;
assign line_index_wire=line_index_initial;

initial
begin
 mem_vhdl_out="usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX";
$hdl_xmr(mem_vhdl_out, line_index_initial, 1);   //line 20
$hdl_xmr(line_index, mem_vhdl_out,1 );
#19680ns;
$hdl_xmr(line_index_initial, mem_vhdl_out,1);
end 
endmodule

I got error as the the source signal type and destination signal type is incompatible at line 20
Please let me know if i have missed anything here,

In reply to Arun_Rajha:

For Try 1) You are not using the correct SystemVerilog syntax. You probably meant

initial
begin
  force usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX = '1b0;
#19680ns;
  release usb_tb.usb_top.c_nk_top.r_mem.WRITE_IDX;
end

But interaction between VHDL and SystemVerilog as well as the system tasks you are using in Try 2) are tool specific. This Mentor sponsored public forum is not for discussing tool specific issues.