Multiple virtual sequencer layers

UVM
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1

Hi,

What is the benefit of having multiple layers of virtual sequences in a UVM environment?
I came across a verification environment that is implemented this way and I can’t see any benefit.
Isn’t it just making things more complicated?

Thanks for any answers and comments in advance,
Peter

2

Hi Peter,

I assume, your question is about subsystem/SoC environment, where the individual IP’s verif. environments are integrated to create a top level env. There are very high chances that the individual IP’s are sufficiently complex that virtual sqr, virtual seq API’s (that helps generate some working scenarios) are part of the delivered VIP itself.
In such cases you cannot avoid having multiple layers. In-fact this layering mechanism will be really useful for you to integrate things at ease.

3

In reply to S.P.Rajkumar.V:

Hi,

Firstly, thank you for your fast comment on this.
Unfortunately this was a module/IP level VE. Although it has many interfaces, I still think that one layer of virtual sequence would have worked perfectly. My guess is that this implementation is a result of misunderstanding the concept UVM.
I see your point of having multiple leayers of virtual sequences when an SoC VE is together reusing the module level ones. Is there any guideline or suggestion by UVM how the connection between the layers should be established?

Regards,
Peter

4

In reply to Peter Simon:

See if these cookbook links about virtual sequence and virtual sequencer helps you.

5

In reply to S.P.Rajkumar.V:

Thank you for the links!
They were very helpful.
Although in this particular case I still think the layering is not required.
Thanks for the help, you made it a lot easier to sort it out!