hello,
class txitem extends uvm_sequence_item;
// factory registration and class constructor
rand write_enable;
rand read_enable;
endclass
from this one sequence item how to write two separate sequences.
in first sequence I need to randomize write_enable.
in second sequence I need to randomize read_enable.
I tried this by disabling rand mode for each variable.
Is there any other method to do this?
thanks