Multiple drivers in always_latch

I have following Code ::


module dummy_dut(input value1, index1);
reg [7:0] data[100];
logic [7:0] value, index ;
always_latch  begin
 // Some Logic Here
 data[index] <= value;
 // ...
end

endmodule


module top;
import uvm_pkg::* ;
`include "uvm_macros.svh"

dummy_dut dut1(value, index);

initial begin
 run_test("dummy_stimulus");
end

// On Uncommenting below I get Error ::  
// Variable '/top/dut1/data[10]' "driven in a combinational block, may not be driven by any other process."
//initial begin
// data[10] = 5;
//end

class dummy_stimulus extends uvm_test;
 `uvm_component_utils(dummy_stimulus)
function new (string name ="stimulus",uvm_component parent =null);
 super.new(name,parent);
endfunction

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   top.dut1.data[5] = 10 ; // Works , but How ?? 
   $display("DATA[%0d]=%0d",5,top.dut1.data[5]);
 endfunction

 task main_phase(uvm_phase phase);
   #10;
   $display("inside main_phase");
 endtask

 endclass

endmodule

My confusion is , since the build_phase() of the test is a seperate process , shouldn’t this be an error too ??

In reply to Have_A_Doubt:

I believe this is a tool specific issue. Some tools are only enforcing the multiple driver rule within RTL code. This Mentor sponsored public forum is not for discussing tool specific issues. Please contact your tool vendor directly for support.