Multiple agents accessing a single uvm_reg_block

Hi,

We have a scenario, where the complete system has one uvm_reg_block. The sytem has two masters driving and accessing any registers at any point of time, but only sequentially.

How to connect sequencers to a single available bus adapter? How does the reg_model know that which master is accessing a register? Can we achieve this by having only one uvm_reg_block or requre two?

When we try to connect two sequencers to the same adapter, only the one connected first works. How to change the sequencer dynamically, if that is possible?

-mpattaje

In reply to mpattaje:

Try this to connect sequencer dynamically… Link.

// Testcase
 
// Set Interface-1 Sequencer to given Register Map
env_cfg.my_reg_block.reg_map.set_sequencer(.sequencer(my_agent1.my_seqr), .adapter( my_env.my_reg_adapter));
 
//Writing with Interface-1
env.my_reg_block.reg_map.MY_REGISTER.write(status, value, UVM_FRONTDOOR);
 
 
// Set Interface-2 Sequencer to given Register Map
env_cfg.my_reg_block.reg_map.set_sequencer(.sequencer(my_agent2.my_seqr), .adapter( my_env.my_reg_adapter));
 
//Writing with Interface-2
env.my_reg_block.reg_map.MY_REGISTER.write(status, value, UVM_FRONTDOOR);

In reply to MayurKubavat:

Thanks Mayur.

But how are you saying that this is dynamic connection? This should happen in build_phase right?

mpattaje