We have a scenario, where the complete system has one uvm_reg_block. The sytem has two masters driving and accessing any registers at any point of time, but only sequentially.
How to connect sequencers to a single available bus adapter? How does the reg_model know that which master is accessing a register? Can we achieve this by having only one uvm_reg_block or requre two?
When we try to connect two sequencers to the same adapter, only the one connected first works. How to change the sequencer dynamically, if that is possible?