In reply to chr_sue:
Thank you for your prompt response. If I understand correctly, you are saying that my register reads should take two cycles. In fact, I do have that requirement when performing read-modify-write type of operations. But how do I model the case where software wants to do a burst read? For example, software could change the read address on every cycle and compensate for the fact that the address is one cycle behind the data. In that case, only the last read would need to take two cycles, all the previous reads could take only one cycle. In my implementation, since I use registered versions of the write address and write enable in my monitor tasks, my data and address always match regardless whether it is a burst read or single read. The drawback, of course, is that I have to maintain two sets of sequence items, one for the reads and one for the writes.