Monitoring register reads and writes

I have a really basic question that I hope somebody can answer. Say, I have a set of registers that I want to write and read on every clock cycle. It seems to me that would require a sequence item per clock cycle, but if that is the case, then the sequence item that monitors and returns the read data would be off by once cycle. In my particular application, in order to get the read data aligned with the read address, I ended up delaying the read address and the write enable by one cycle. That works great, but now my monitor has to deal with two sets of sequence items, one for the writes and one for the reads. Although this works, I suspect there is a better way of doing this. Can somebody please explain what that is?

In reply to RaulAguilarPA:

Your testbench should not define the protocol of your DUT interfaces. In your case your bus cycle has 1 clock cycle. You need a cycle to write the data and you need another clock cycle to read the data. If you want to read from the same address your address signal has to become 2 cycles long.

In reply to chr_sue:

Thank you for your prompt response. If I understand correctly, you are saying that my register reads should take two cycles. In fact, I do have that requirement when performing read-modify-write type of operations. But how do I model the case where software wants to do a burst read? For example, software could change the read address on every cycle and compensate for the fact that the address is one cycle behind the data. In that case, only the last read would need to take two cycles, all the previous reads could take only one cycle. In my implementation, since I use registered versions of the write address and write enable in my monitor tasks, my data and address always match regardless whether it is a burst read or single read. The drawback, of course, is that I have to maintain two sets of sequence items, one for the reads and one for the writes.

In reply to RaulAguilarPA:

I did not say a read lasts 2 cycles. Finally it depends what your interface protocol requires. A burst read does not mean the data are valid in the same cycle as the address has been supplied. Look at a DDR memory. There is quite a number of cycles in between providing the cmd and the address and getting the read data. And I do not believe you have to use different seq_items for read and write. You can cover reads and writes with thhe same seq_item.