Hello,
I have a UVM testbench and I have a requirement to create an IVC for a combinatorial interface with zero delay. In the sense that the DUT sends a 6-bit signal out to the TB and TB should respond with a 2-bit data in the same cycle. Any ideas how to create an IVC which correctly samples for both driving the response and also gives out the item correctly (as seen on the waveform) for checker ?
As I do not have a signal to tell me when the request from the DUT is valid, I have asked a “verification only signal” which acts as a valid. Using this SO CALLED VALID signal, I could sample the interface as below.
if(inf.dut_valid)
item.dut_index = inf.dut_index;
and in the driver, after getting the item, driving
inf.tb_return_data <= item.tb_return_data
with this work-around, I could see the response being generated on the same clock cycle as the dut gives a request. However, the monitored item has tb_return_data from the previous cycle. I do not understand why ? Can anyone explain ? I am stuck.
The issue is the same monitor has to feed to sequence to enable driving tb_return_data and the same monitor has to feed to scoreboard to be fed to reference model.
Thanks,
Madhu