Modeling registers of a chip

Hello,

I have a DUT with an SPI interface (master) reading and writing to the registers of an IC. I have created an environment to test the DUT. I have used the SPI QVIP (slave) of Mentor. Now I need to model the behaviour of registers of IC and respond to the DUT when it tries to read or write to the registers.

What is the best method to model this registers of IC in the UVM environment?

Thanks.

In reply to rdemirci:

Have you read the UVM Cookbook chapter on Registers?

In reply to cgales:

Thank you for your reply.
Yes, I read. That chapter is creating a RAL model to access the registers in DUT. I have this kind of a model in my environment for the registers in DUT. But my requirement is to create a model to mimic the chip registers that my DUT is accessing. I am not sure if I can use the same functionality for this.

In reply to rdemirci:

I’m not clear on what you are trying to accomplish. If you have a register model for your DUT, then you can re-use this register model for higher level verification. If you don’t need to access the registers from your UVM environment, then there is no need to create a register model for them, although you can if you want.

Perhaps if you can explain what you need to accomplish someone can provide a better answer.

In reply to rdemirci:

The UVM register layer is not only to provide access to the registers in DUT. It is mirror of your DUT registers. If you need register content for instance in a scoreboard, you can simply get this from the testbench without executing a bus access to get the register value from the DUT registers. Additionally the UVM register layer is providing capabilities to hold both models synchronous.

In reply to cgales:

My DUT is accessing a CAN-IC in real world to read/write its registers. I generated a register model for the registers in my DUT. Now I want to model the registers in the CAN-IC to access them via SPI QVIP. These registers are not in my DUT and will only mimic the real CAN-IC that my DUT is accessing.

In reply to rdemirci:

My environment:

------------------     ----------     ---------     --------------     -----------------
| Register Model |     | Custom |     |       |     |            |     |  IC Register  |
| for DUT        |<--->|  VIP   |<--->|  DUT  |<--->|  SPI QVIP  |<--->|  Model that   |
|                |     |        |     |       |     |            |     |   I need      |
------------------     ----------     ---------     --------------     -----------------

In reply to rdemirci:

I’m getting confused viewing your figure.
I try to ask a few questions to get some more specific information.

  1. Your DUT has regsietres inside you want to access from testbench?
  2. What kind of register model do you have? a UVM model or something else.
  3. Whatis VIP?
  4. SPI QVIP is a UVM VIP.
  5. Dou you have additional interfaces?
  6. Are you accessing your DUT-internal registers through the SPI interface?

Would be grear if you could answer my questions.

In reply to chr_sue:

Hi chr_sue,

The figure is not previewed as I entered, sorry.

To describe my env.:
1- My DUT has two interfaces: Custom and SPI.
2- I am accessing the DUT registers via custom interface. I developed a register model (RAL) to access DUT registers via frontdoor access. I am using a custom VIP for this interface.
3- My DUT is accessing a CAN-IC via SPI interface and writing/reading CAN_IC registers. Here my DUT is SPI master. I am using SPI Questa VIP (VIP from Mentor) for SPI interface.
4- I need a model to mimic CAN-IC registers that my DUT can reach. Here SPI VIP will use this model.

For your questions:
1- Yes. I already developed a register model for them for access via custom i/f.
2- UVM Register Abstraction Layer model.
3- Verification IP
4- QVIP (Questa Verification IP)
5- Yes, SPI and custom i/f.
6- No, through custom i/f.

Thanks.

In reply to rdemirci:

There shouldn’t be any difference between hooking up a monitor for your custom interface to the register model for your DUT and hooking up a CAN monitor to the register model for your off-chip registers. The only exotic thing here is extracting the information about what address is being accessed and with what data from a CAN frame (i.e. writing a CAN ↔ regs adapter).

You probably have some entries in your spec that define formats for your CAN frames: bits[x:y] are the address, bits[z:t] are the data, bit[u] says if it’s a register read or a write. You’ll have to convert these rules into code for the register adapter.