I am currently modeling a pipe-lined out of order transaction driver to implement write burst in AXI 4.0. I have created 2 drivers 1 for driving the address related signals(i.e. AWADDR,AWVALID, AWBURST, AWSIZE) named "AXI_master_address_driver". Another driver is named "AXI_master_data_driver" and it is used for driving data realated signals (i.e. WDATA, WVALID etc). This driver also drives BREADY signal and collects BRESP from slave.
Slave also has 2 drivers one named (slave_resp_driver) is for driving AWREADY and collecting Address related info. And second is for driving the data related signals WREADY and collect data related signals is named as slave_data_driver. The address related info which was collected in the frist driver is sent to the second driver via a mailbox and the second driver writes the WDATA sent from master in a memory RAM address.
Now I can not implement the pipelined operation for address and data.
How should I model these drivers? Any recommendations will be very helpful as I have very less idea regarding out of order transaction driver modeling.