Modeling pipelined out of order transaction driver in UVM for AXI 4.0

UVM
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I am currently modeling a pipe-lined out of order transaction driver to implement write burst in AXI 4.0. I have created 2 drivers 1 for driving the address related signals(i.e. AWADDR,AWVALID, AWBURST, AWSIZE) named “AXI_master_address_driver”. Another driver is named “AXI_master_data_driver” and it is used for driving data realated signals (i.e. WDATA, WVALID etc). This driver also drives BREADY signal and collects BRESP from slave.

Slave also has 2 drivers one named (slave_resp_driver) is for driving AWREADY and collecting Address related info. And second is for driving the data related signals WREADY and collect data related signals is named as slave_data_driver. The address related info which was collected in the frist driver is sent to the second driver via a mailbox and the second driver writes the WDATA sent from master in a memory RAM address.

Now I can not implement the pipelined operation for address and data.

How should I model these drivers? Any recommendations will be very helpful as I have very less idea regarding out of order transaction driver modeling.

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In reply to farshad112:

To create a pipelined driver you can use a semaphore to synchronize the control and data phases of data transfers.

Check this cookbook link on pipelined driver to understand the implementation.

Note that the above implementation doesn’t take care of out-of-ordering. It need to be taken care of.

3

In reply to S.P.Rajkumar.V:

@S.P.Rajkumar.V
Thanks for your reply.
Then how should I take care of out of order transactions. I understand that using semaphore to model pipelined driver works fine for protocols like AHB. But for AXI I could not understand how to implement this technique. A detailed answer on how to take care of this out of order transactions would be very helpful.

Thanks,
FARSHAD

4

Can anyone tell, how to implement cache concept in axi verification ip? Is cache concept required in VIP to verify complete protocol(like to verify cacheable,bufferable concept)??

Thanks in advance!!!

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In reply to farshad112:

Out of order if functionality of slave , it can send the response in any order but for same AXID responses should be in order. There must be independent thread for collecting the response and identifier of that response must be BID .

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In reply to farshad112:

What do you want to model a pipelined or an out-of-order transfer? Forr the pipelined transfer follow the example in the UVM Cookbook. For an out-of-order transfer it is more complicated and additional details are required to give you a reasonable advice.