Mismatch between read and mirrored value

UVM
,
1

Hi ,

I do a write(status,1000) on a register ( which is a shift register with access RW ) followed by read(status,rd_data ) .
I notice that it throws a uvm_error due to mismatch . I notice that it expects the value to be same as written .

The issue is since its a shift register the value shifts after the initial value ( write value ) is provided so the value read is the current value of the register .

Any suggestions how can I overcome this ?

In the env :: I have reg_block.default_map.auto_predict(1) , could this play a role ?

Thanks ,

2

In reply to MICRO_91:

If the WR shifts your register by 1 step. You have to read from the last addressand not from the actual one.

3

In reply to chr_sue:

Hi ,

Could you elaborate ?

The chain of events is as follows ::

(1) I have ctrl register at address 0x40 . If this is high ( write(status,1) ) then the register will shift

(2) I have a shift register ( Actually a LFSR ) at address 0x44 . the value written into it acts as initial seed . Since ctrl_reg is high ( due to write(1) at address 0x40 previously ) for successive clocks it shifts data ( the seed written into it ) based on some polynomial .
The write occurs at address 0x44 , so does the read .

Thanks

4

In reply to MICRO_91:

Please show real code, and actual error messages.

You stated your register is configured as “RW”, and it would seem you have enabled read checking ( by calling uvm_reg_map::set_check_on_read ). In addition to that, in order to get this error, your register field must be configured as non-volatile, and you haven’t installed a cycle accurate predictor.

Your solutions are to either, install a predictor for this register, change the field configuration to volatile, disable field comparison via uvm_reg_field::set_compare(UVM_NO_CHECK), or to disable read checking ( uvm_reg_map::set_check_on_read(0) ).

If you are running with uvm_reg_map::set_check_on_read(1), the assumption is you are installing predictors that keep the model with an up-to-date prediction of all non-volatile registers at all times. Is that what you expect?

I can imagine predicting the exact value of this register could very difficult, so you may just want to change it’s configuration to volatile when it’s created. This also puts the field in the UVM_NO_CHECK state. Alternatively, you could dynamically control the check state. Say by disabling checking when the LSFR is enabled, and re-enabling when the LSFR is disabled after the mirror is updated.

Assuming this is not the mechanism by which you are verifying the LSFR polynomial itself, I’d probably configure it to be volatile when it’s created.

5

In reply to warnerrs:

Hi ,

The error I get is ::

UVM_ERROR @ 472250000: reporter [RegModel] Register “env_h_rm.abc_regs.data” value read from DUT (0x00000000000000000000000000000000000000000000000000000000a6cd82d5) does not match mirrored value (0x000000000000000000000000000000000000000000000000000000007e16ac27)

I have the following declaration ::


 class lfsr_data extends uvm_reg ;
  rand uvm_reg_field data ;
 
   function void build() ;
      
     data = uvm_reg_field::type_id::create("data");
     data.configure(this,32,0,"RW",0,32'd0,1,1,1); // Volatile is 0 
     data.set_compare(UVM_CHECK);
  
   endfunction

// In reg_block
    rand lfsr_data data ;
// In reg_block's build() function 
    default_map = create_map("default_map",0,4,UVM_BIG_ENDIAN,1) ;
    default_map.set_check_on_read();
     .......
    data = lfsr_data::type_id::create("data");
    data.configure(this,null,"data");
    data.build();
    default_map.add_reg(data,'h12,"RW");

I have to use above code as it is , without any modification .

Could you please elaborate on cycle level predictor ?

Also how do I dynamically change the check state ? ( Cos if I randomly write(1) into ctrl register I would like to disable the read and avoid the error )

Thanks