Mirror value is not getting updated after read/write using reg model

UVM
, ,
1

Hi,

I have integrated reg model and able to do read/write on registers. But mirror value is not getting updated with latest value after read/write.
When I am doing mirror(status, UVM_CHECK); I am getting below error message.

“value read from DUT (0x0000000000000008) does not match mirrored value (0x0000000000000000)”

I have done below things in my env.

reg_model.build();
reg_model.lock_model();
reg_model.reset();
reg_model.default_map.set_auto_predict(1);

I am using UVM version uvm-1.1d

Am I missing anything? Or can someone please help me out if I need to do something specific to get it resolved?

Thanks,
Devang