Method to pass data across UVM sequences

Let’s say I have 2 sequences (read and write to verify a memory). The sequence_item transaction may have an address and a data field. How would I communicate this transaction data generated as part of one sequence to the other sequence. Let us say, the write sequence generates it and the read sequence may use the data from the write sequence or generate its own.

How would this transaction data transfer happen in these two different cases - 1.Both sequences running on the same sequencer 2.Both sequences running on different sequencers

The answer might be subjective, but what would be the ideal way?

You can use a virtual sequence.

In reply to absingh:

Can you provide an example to illustrate?
A virtual sequence manages execution of 2 sub sequences. Not facilitate data transfer between them.

  1. Populate the req/rsp fields of a transaction so the other sequence can pick up the same.

  2. Pass data through an analysis port in the monitor and through the sequencer into the sequence for the other sequence to access previous data.

  3. If there are 2 different sequencers, make the connection in the env to pass the data over.

In reply to kernalmode1:

[For the same sequencer]
Both Sequences communicated with the same Driver, so driver can be the contact point. I mean driver can remember the write address than when receiving read sequence read from that same address.

Or you can make master-slave type sequences Write will be master sequence, which after finishing will trigger Read sequence.

And next way, is using sequencer. It can keep/remember the address values and driver can get it from there.

Or use configure class, each time put the write address parameter there using driver, and during read sequence get from there.

[For the different sequencer]
I think there you use 2 different agents, than may be it is not a good idea to share info from one sequence to another.
Revise the test-architecture. Something should be wrong.