Hi there,
I read the UVM cook book about uvm memory model, it says, quoted as below:
Unlike registers, memory values are not stored because of the workstation memory overhead involved.
What does it mean by “memory values are not stored”? If I would like to use a storage to store some configuration data for my DUT, does it mean that I cannot use a uvm_mem object to store these configurations?
Also, if no data is stored in the uvm_mem object, what happens when I read from the uvm_mem object?
The registers of a design are mirrored in the UVM testbench. Memory is not mirrored due to memory overhead of your workstation. But UVM is providing you mechanisms to deal with memories in an easy way.
In this case, if my DUT doesn’t have a memory but the interface of the DUT will interact with a memory which is in my testbench env, do I need to use uvm_mem or just write up a memory class myself to respond the read/write requests from the DUT?
In reply to rma:
Yes, you can just write up a memory class. uvm_mem and uvm_reg are for interacting with memories and registers inside your DUT. See Sequences/Slave | Verification Academy