Materials for Basic Verification Course

UVM
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Hi All,
I am working with a team on building basic verification academic course for last year Computer Engineering student.
The course length is 3 months 3-4 daily hours course.

The course’s purpose is to give the student basic knowledge/technical skill in verification, that give them a better chance to compete on junior verification engineers jobs.

The topics that we see them relevant are :

  1. VLSI introduction & Basics of Chip design flow (1WK)
  2. Verilog basics (1WK)
  3. Introduction to verification and basic concepts (1WK)
  4. Verification techniques (1WK)
  5. System Verilog and UVM (3WK)
  6. Specman (3WK)

In verificationacademy web the materials exist as different courses, I believe such a basic course was held many times.
could you help find materials for such a course that includes practical exercise.

please advise!

2

First lesson: “SystemVerilog” is one word. ;-)

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In reply to khaledma85:

This is interesting to me because I just had a discussion with a professor at UC Irvine who teaches SystemVerilog about the lack of verification topics covered for computer engineering students. Even my own son (who just graduated from Harvey Mudd, a leading engineering school in the US), barely had time in his curriculum to get through a SystemVerilog design course.

I think the problem is not limited to computer engineering. Students need to be taught design and verification concepts together for any engineering discipline, and that could be a whole course in itself. Its about a process that begins gathering requirements, creating a specification, and following that through to an end product that meets those original requirements. The classic tree/tire swing comic illustrates this brilliantly.

So trying to cram your curriculum into single course looking for practical examples seems impractical to me.

4

In reply to dave_59:

  1. This type of course for preparation for a real job is typically not available in the US.
  2. It is however, widely available in India; they call it “incubation”. In fact, my co-author Srini is providing such courses.
  3. I fully agree with Dave’s comments “Its about a process that begins gathering requirements, creating a specification, and following that through to an end product that meets those original requirements.”
  4. In your course curriculum, you need to add the topic of assertions.
  5. Though biased and self-serving, I wrote several books on assertions. My last book SVA Handbook 4th Edition, 2016 addresses the topic of assertions and methodologies (e.g.,how to write requirement and verification specs, defining contraints, etc) all my complete examples. Many models also include the use of advanced SystemVerilog features as supporting logic for the assertions; these include queues, associative arrays. Please see the TOC at Amazon.com
    The book is also available in India (for the Asian market) at a reduced cost (contact Home - My cvcblr ). Contact me for a 32% discount code.
  6. My paper on Assertions provides an insight in how assertions work in SVG. It is entitled “PAPER: Understanding the SVA Engine + Simple alternate solutions”
    PAPER: Understanding the SVA Engine + Simple alternate solutions | Verification Academy

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115