Matching types in Parameterized Class

UVM
,
1

Hi all ,


SV LRM  8.25  :: 

   "A specialization is the combination of a specific generic class with a unique set of parameters. Two sets of
    parameters shall be unique unless all parameters are the same, as defined by the following rules:

    a) A parameter is a type parameter and the two types are matching types.
    b) A parameter is a value parameter and both their type and their value are the same."



 Since uvm_config_db is a Parameterized class , I was trying codes to check if the set() N get() calls work with matching types !!


`include "uvm_pkg.sv"
`include "uvm_macros.svh" 

import uvm_pkg::*;

`define COMP_NEW function new ( string name , uvm_component parent ) ; \
                  super.new(name,parent);\
                 endfunction

 class agent extends uvm_agent ;

 `uvm_component_utils( agent ) 
 `COMP_NEW

  function void build_phase ( uvm_phase phase ) ;
   int active;
    
    `uvm_info(get_name(),"In build_phase",UVM_NONE)
     
  	 if ( get_config_int("is_active",active) )  // NOTE :: Deprecated from UVM 1.2 !!    
       begin	 
  	 
         `uvm_info(get_name()," get_config_int is Successful !! ",UVM_NONE)
      	   is_active = uvm_active_passive_enum'(active);
          
         `uvm_info(get_name(),{" agent is  ", ( (is_active) ? "UVM_ACTIVE" : "UVM_PASSIVE" ) },UVM_NONE) // typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum ;
       
       end
  	
  
  endfunction


 endclass


 typedef reg signed [4095:0] my_type ;

 class test extends uvm_component ;

 `uvm_component_utils( test ) 
 `COMP_NEW

  agent ag ;

  function void build_phase ( uvm_phase phase ) ;
    `uvm_info(get_name(),"In build_phase",UVM_NONE)
	 
	 uvm_config_db#(my_type)::set(uvm_top,"*","is_active",100) ; // Value of 100 set i.e Passive ( Since LSB is 0 )  !! !! 
	 ag = new("ag",this) ; 
  endfunction

  function void end_of_elaboration_phase ( uvm_phase phase ) ;
     uvm_top.print_topology();
  endfunction
 
 
 endclass

I observe that get() is Unsuccessful

Since uvm_bit_stream_t is actually logic signed [4095:0]

Shouldn’t reg signed [4095:0] work ?
( Since both are matching types i.e both are 4-state , Same Sized , Same Packed Range )

2

In reply to MICRO_91:

Section 6.22.1 Matching types
Two data types shall be defined as matching data types using the following inductive definition. If two data types do not match using the following definition, then they shall be defined to be nonmatching.
e) A simple bit vector type that does not have a predefined width and one that does have a predefined width match if both are 2-state or both are 4-state, both are signed or both are unsigned, both have the same width, and the range of the simple bit vector type without a predefined width is [width–1:0].

In your example, the two types are not both signed or both unsigned, so the types do not match.

3

In reply to dave_59:

Since uvm_bitsream_t is declared as ::

**typedef logic signed [ UVM_STREAMBITS - 1 : 0 ] uvm_bitstream_t ;

( by default UVM_STREAMBITS is 4096 )**

I declared my_type as reg signed [4095:0] .

Now both are signed , both have same size and both have same range

Yet it doesn’t work

4

In reply to MICRO_91:

You have run into a simulator specific issue. The LRM says “logic and reg denote the same type”. Your tool is not following that.