Hello,
I am new to UVM. I am not able to write Driver and Monitor, with maintaining data integrity between them. I am not able to visualise when a signal is being driven and collected from interface. Please help me in overcoming this problem.
In reply to suryanilkumar:
Can you explain what you are having difficulty with?
The driver and monitor should be two separate components with no communication between them. This is done to maximize re-use of the UVC agent. The driver should control the interface signals per the protocol specification and provided sequence item, and the monitor should watch the interface signals and generate a sequence item per the protocol.
In reply to suryanilkumar:
when a signal is being driven and collected from interface
This depends on the bus protocol you are using. If you are clear with the communication protocol being used, you will not have any issues visualizing timing requirements.
write Driver and Monitor, with maintaining data integrity between them
Also, you do not check data integrity between Driver and Monitor components (As there is no communication between them). You can have protocol checks in monitor to see if data on interface is valid. Data integrity checks are mainly for design input(Input monitor) and design output(Output monitor).